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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2003/08/08 16:36:33 tadejm
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// Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure.
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//
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// Revision 1.3 2003/03/26 13:16:18 mihad
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// Revision 1.3 2003/03/26 13:16:18 mihad
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// Added the reset value parameter to the synchronizer flop module.
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// Added the reset value parameter to the synchronizer flop module.
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// Added resets to all synchronizer flop instances.
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// Added resets to all synchronizer flop instances.
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// Repaired initial sync value in fifos.
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// Repaired initial sync value in fifos.
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//
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//
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inGreyCount <= #`FF_DELAY inNextGreyCount ;
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inGreyCount <= #`FF_DELAY inNextGreyCount ;
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end
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end
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wire [(PCIW_ADDR_LENGTH-2):0] wb_clk_sync_inGreyCount ;
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wire [(PCIW_ADDR_LENGTH-2):0] wb_clk_sync_inGreyCount ;
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reg [(PCIW_ADDR_LENGTH-2):0] wb_clk_inGreyCount ;
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reg [(PCIW_ADDR_LENGTH-2):0] wb_clk_inGreyCount ;
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synchronizer_flop #((PCIW_ADDR_LENGTH - 1), 0) i_synchronizer_reg_inGreyCount
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pci_synchronizer_flop #((PCIW_ADDR_LENGTH - 1), 0) i_synchronizer_reg_inGreyCount
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(
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(
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.data_in (inGreyCount),
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.data_in (inGreyCount),
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.clk_out (wb_clock_in),
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.clk_out (wb_clock_in),
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.sync_data_out (wb_clk_sync_inGreyCount),
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.sync_data_out (wb_clk_sync_inGreyCount),
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.async_reset (pciw_clear)
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.async_reset (pciw_clear)
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