| Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.1 2003/01/27 16:49:31 mihad
|
|
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
|
|
//
|
// Revision 1.10 2002/10/18 03:36:37 tadejm
|
// Revision 1.10 2002/10/18 03:36:37 tadejm
|
// Changed wrong signal name scanb_sen into scanb_en.
|
// Changed wrong signal name scanb_sen into scanb_en.
|
//
|
//
|
// Revision 1.9 2002/10/17 22:51:08 tadejm
|
// Revision 1.9 2002/10/17 22:51:08 tadejm
|
// Changed BIST signals for RAMs.
|
// Changed BIST signals for RAMs.
|
| Line 559... |
Line 562... |
else
|
else
|
if (in_count_en)
|
if (in_count_en)
|
inGreyCount <= #`FF_DELAY inNextGreyCount ;
|
inGreyCount <= #`FF_DELAY inNextGreyCount ;
|
end
|
end
|
|
|
|
wire [(PCIW_ADDR_LENGTH-2):0] wb_clk_sync_inGreyCount ;
|
|
reg [(PCIW_ADDR_LENGTH-2):0] wb_clk_inGreyCount ;
|
|
synchronizer_flop #((PCIW_ADDR_LENGTH - 1)) i_synchronizer_reg_inGreyCount
|
|
(
|
|
.data_in (inGreyCount),
|
|
.clk_out (wb_clock_in),
|
|
.sync_data_out (wb_clk_sync_inGreyCount),
|
|
.async_reset (1'b0)
|
|
) ;
|
|
|
|
always@(posedge wb_clock_in or posedge pciw_clear)
|
|
begin
|
|
if (pciw_clear)
|
|
wb_clk_inGreyCount <= #`FF_DELAY 1 ;
|
|
else
|
|
wb_clk_inGreyCount <= # `FF_DELAY wb_clk_sync_inGreyCount ;
|
|
end
|
|
|
always@(posedge wb_clock_in or posedge pciw_clear)
|
always@(posedge wb_clock_in or posedge pciw_clear)
|
begin
|
begin
|
if (pciw_clear)
|
if (pciw_clear)
|
begin
|
begin
|
outGreyCount[(PCIW_ADDR_LENGTH-2)] <= #`FF_DELAY 1'b1 ;
|
outGreyCount[(PCIW_ADDR_LENGTH-2)] <= #`FF_DELAY 1'b1 ;
|
| Line 589... |
Line 610... |
else
|
else
|
if (out_count_en)
|
if (out_count_en)
|
pciw_outTransactionCount <= #`FF_DELAY pciw_outTransactionCount + 1'b1 ;
|
pciw_outTransactionCount <= #`FF_DELAY pciw_outTransactionCount + 1'b1 ;
|
end
|
end
|
|
|
// transaction is ready when incoming transaction count is not equal to outgoing transaction count ( what comes in must come out )
|
assign pciw_transaction_ready_out = wb_clk_inGreyCount != outGreyCount ;
|
// anytime last entry of transaction is pulled out of fifo, transaction ready flag is cleared for at least one clock to prevent wrong operation
|
|
// ( otherwise transaction ready would stay set for one additional clock even though next transaction was not ready )
|
|
|
|
wire pciw_transaction_ready_flop_i = inGreyCount != outGreyCount ;
|
|
meta_flop #(0) i_meta_flop_transaction_ready
|
|
(
|
|
.rst_i (pciw_clear),
|
|
.clk_i (wb_clock_in),
|
|
.ld_i (out_count_en),
|
|
.ld_val_i (1'b0),
|
|
.en_i (1'b1),
|
|
.d_i (pciw_transaction_ready_flop_i),
|
|
.meta_q_o (pciw_transaction_ready_out)
|
|
) ;
|
|
|
|
assign pcir_transaction_ready_out = 1'b0 ;
|
assign pcir_transaction_ready_out = 1'b0 ;
|
|
|
endmodule
|
endmodule
|
|
|
