| Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.7 2003/01/27 16:49:31 mihad
|
|
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
|
|
//
|
// Revision 1.6 2003/01/21 16:06:56 mihad
|
// Revision 1.6 2003/01/21 16:06:56 mihad
|
// Bug fixes, testcases added.
|
// Bug fixes, testcases added.
|
//
|
//
|
// Revision 1.5 2002/08/22 13:28:04 mihad
|
// Revision 1.5 2002/08/22 13:28:04 mihad
|
// Updated for synthesis purposes. Gate level simulation was failing in some configurations
|
// Updated for synthesis purposes. Gate level simulation was failing in some configurations
|
| Line 81... |
Line 84... |
bc_in,
|
bc_in,
|
bc0_in,
|
bc0_in,
|
data_in,
|
data_in,
|
data_out,
|
data_out,
|
be_in,
|
be_in,
|
|
next_be_in,
|
req_in,
|
req_in,
|
rdy_in,
|
rdy_in,
|
addr_phase_in,
|
addr_phase_in,
|
bckp_devsel_in,
|
bckp_devsel_in,
|
bckp_trdy_in,
|
bckp_trdy_in,
|
| Line 137... |
Line 141... |
pcir_fifo_empty_in,
|
pcir_fifo_empty_in,
|
pciw_fifo_wenable_out,
|
pciw_fifo_wenable_out,
|
pciw_fifo_addr_data_out,
|
pciw_fifo_addr_data_out,
|
pciw_fifo_cbe_out,
|
pciw_fifo_cbe_out,
|
pciw_fifo_control_out,
|
pciw_fifo_control_out,
|
|
pciw_fifo_three_left_in,
|
pciw_fifo_two_left_in,
|
pciw_fifo_two_left_in,
|
pciw_fifo_almost_full_in,
|
pciw_fifo_almost_full_in,
|
pciw_fifo_full_in,
|
pciw_fifo_full_in,
|
wbw_fifo_empty_in,
|
wbw_fifo_empty_in,
|
wbu_del_read_comp_pending_in,
|
wbu_del_read_comp_pending_in,
|
| Line 210... |
Line 215... |
input [3:0] bc_in ; // current request bus command input - registered
|
input [3:0] bc_in ; // current request bus command input - registered
|
input bc0_in ; // current cycle RW signal
|
input bc0_in ; // current cycle RW signal
|
output [31:0] data_out ; // for read operations - current dataphase data output
|
output [31:0] data_out ; // for read operations - current dataphase data output
|
input [31:0] data_in ; // for write operations - current request data input - registered
|
input [31:0] data_in ; // for write operations - current request data input - registered
|
input [3:0] be_in ; // current dataphase byte enable inputs - registered
|
input [3:0] be_in ; // current dataphase byte enable inputs - registered
|
|
input [3:0] next_be_in ; // next dataphase byte enable inputs - NOT registered
|
// Port connection control signals from PCI FSM
|
// Port connection control signals from PCI FSM
|
input req_in ; // Read is requested to WB master from PCI side
|
input req_in ; // Read is requested to WB master from PCI side
|
input rdy_in ; // DATA / ADDRESS selection from PCI side when read or write - registered
|
input rdy_in ; // DATA / ADDRESS selection from PCI side when read or write - registered
|
input addr_phase_in ; // Indicates address phase and also fast-back-to-back address phase - registered
|
input addr_phase_in ; // Indicates address phase and also fast-back-to-back address phase - registered
|
input bckp_devsel_in ; // DEVSEL input (which is registered) equivalent
|
input bckp_devsel_in ; // DEVSEL input (which is registered) equivalent
|
| Line 283... |
Line 289... |
input pcir_fifo_almost_empty_in ; // almost empty indicator from PCIR_FIFO
|
input pcir_fifo_almost_empty_in ; // almost empty indicator from PCIR_FIFO
|
input pcir_fifo_empty_in ; // empty indicator
|
input pcir_fifo_empty_in ; // empty indicator
|
|
|
// PCIW_FIFO control signals used for sinking data into PCIW_FIFO and status monitoring
|
// PCIW_FIFO control signals used for sinking data into PCIW_FIFO and status monitoring
|
output pciw_fifo_wenable_out ; // write enable output to PCIW_FIFO
|
output pciw_fifo_wenable_out ; // write enable output to PCIW_FIFO
|
|
wire pciw_fifo_wenable ; // not registered we
|
output [31:0] pciw_fifo_addr_data_out ; // address / data output signals to PCIW_FIFO
|
output [31:0] pciw_fifo_addr_data_out ; // address / data output signals to PCIW_FIFO
|
output [3:0] pciw_fifo_cbe_out ; // command / byte enable signals to PCIW_FIFO
|
output [3:0] pciw_fifo_cbe_out ; // command / byte enable signals to PCIW_FIFO
|
output [3:0] pciw_fifo_control_out ; // control signals to PCIW_FIFO
|
output [3:0] pciw_fifo_control_out ; // control signals to PCIW_FIFO
|
|
input pciw_fifo_three_left_in ; // three data spaces left in PCIW_FIFO
|
input pciw_fifo_two_left_in ; // two data spaces left in PCIW_FIFO
|
input pciw_fifo_two_left_in ; // two data spaces left in PCIW_FIFO
|
input pciw_fifo_almost_full_in ; // almost full indicator from PCIW_FIFO
|
input pciw_fifo_almost_full_in ; // almost full indicator from PCIW_FIFO
|
input pciw_fifo_full_in ; // full indicator from PCIW_FIFO
|
input pciw_fifo_full_in ; // full indicator from PCIW_FIFO
|
|
|
// WBW_FIFO empy control signal used when delayed read is complete in PCIR_FIFO
|
// WBW_FIFO empy control signal used when delayed read is complete in PCIR_FIFO
|
| Line 777... |
Line 785... |
// when '1', the bus command is IO command - not supported commands are checked in pci_decoder modules
|
// when '1', the bus command is IO command - not supported commands are checked in pci_decoder modules
|
wire io_memory_bus_command = !norm_bc[3] && !norm_bc[2] ;
|
wire io_memory_bus_command = !norm_bc[3] && !norm_bc[2] ;
|
assign disconect_wo_data_out = (
|
assign disconect_wo_data_out = (
|
((/*pcir_fifo_ctrl[`LAST_CTRL_BIT] ||*/ pcir_fifo_empty_in || ~burst_ok_out/*addr_burst_ok*/ || io_memory_bus_command) &&
|
((/*pcir_fifo_ctrl[`LAST_CTRL_BIT] ||*/ pcir_fifo_empty_in || ~burst_ok_out/*addr_burst_ok*/ || io_memory_bus_command) &&
|
~bc0_in && ~frame_reg_in) ||
|
~bc0_in && ~frame_reg_in) ||
|
((pciw_fifo_full_in || pciw_fifo_almost_full_in || next_write_to_pciw_fifo_is_last || (pciw_fifo_two_left_in && pciw_fifo_wenable_out) || ~addr_burst_ok || io_memory_bus_command) &&
|
((pciw_fifo_full_in || pciw_fifo_almost_full_in || next_write_to_pciw_fifo_is_last || pciw_fifo_two_left_in ||
|
|
(pciw_fifo_three_left_in && pciw_fifo_wenable) || ~addr_burst_ok || io_memory_bus_command) &&
|
bc0_in && ~frame_reg_in)
|
bc0_in && ~frame_reg_in)
|
) ;
|
) ;
|
assign disconect_w_data_out = (
|
assign disconect_w_data_out = (
|
( burst_ok_out && !io_memory_bus_command && ~bc0_in ) ||
|
( burst_ok_out && !io_memory_bus_command && ~bc0_in ) ||
|
( addr_burst_ok && !io_memory_bus_command && bc0_in )
|
( addr_burst_ok && !io_memory_bus_command && bc0_in )
|
| Line 828... |
Line 837... |
|
|
always@(posedge clk_in or posedge reset_in)
|
always@(posedge clk_in or posedge reset_in)
|
begin
|
begin
|
if (reset_in)
|
if (reset_in)
|
next_write_to_pciw_fifo_is_last <= #1 1'b0 ;
|
next_write_to_pciw_fifo_is_last <= #1 1'b0 ;
|
else if (next_write_to_pciw_fifo_is_last && pciw_fifo_wenable_out)
|
else if (next_write_to_pciw_fifo_is_last && pciw_fifo_wenable)
|
next_write_to_pciw_fifo_is_last <= #1 1'b0 ;
|
next_write_to_pciw_fifo_is_last <= #1 1'b0 ;
|
else if (pciw_fifo_wenable_out && disconect_wo_data_out)
|
else if (pciw_fifo_wenable && disconect_wo_data_out)
|
next_write_to_pciw_fifo_is_last <= #1 1'b1 ;
|
next_write_to_pciw_fifo_is_last <= #1 1'b1 ;
|
end
|
end
|
|
|
// signal assignments from fifo to PCI Target FSM
|
// signal assignments from fifo to PCI Target FSM
|
assign wbw_fifo_empty_out = wbw_fifo_empty_in ;
|
assign wbw_fifo_empty_out = wbw_fifo_empty_in ;
|
assign wbu_del_read_comp_pending_out = wbu_del_read_comp_pending_in ;
|
assign wbu_del_read_comp_pending_out = wbu_del_read_comp_pending_in ;
|
assign pciw_fifo_full_out = (pciw_fifo_full_in || pciw_fifo_almost_full_in || pciw_fifo_two_left_in) ;
|
assign pciw_fifo_full_out = (pciw_fifo_full_in || pciw_fifo_almost_full_in || pciw_fifo_two_left_in || pciw_fifo_three_left_in) ;
|
assign pcir_fifo_data_err_out = pcir_fifo_ctrl[`DATA_ERROR_CTRL_BIT] && !sel_conf_fifo_in ;
|
assign pcir_fifo_data_err_out = pcir_fifo_ctrl[`DATA_ERROR_CTRL_BIT] && !sel_conf_fifo_in ;
|
// signal assignments to fifo
|
// signal assignments to PCIR FIFO fifo
|
assign pcir_fifo_flush_out = pcir_fifo_flush_reg ;
|
assign pcir_fifo_flush_out = pcir_fifo_flush_reg ;
|
assign pcir_fifo_renable_out = fetch_pcir_fifo_in && !pcir_fifo_empty_in ;
|
assign pcir_fifo_renable_out = fetch_pcir_fifo_in && !pcir_fifo_empty_in ;
|
assign pciw_fifo_wenable_out = load_to_pciw_fifo_in ;
|
|
assign pciw_fifo_control_out[`ADDR_CTRL_BIT] = ~rdy_in ;
|
// signal assignments to PCIW FIFO
|
assign pciw_fifo_control_out[`BURST_BIT] = rdy_in ? ~frame_reg_in : 1'b0 ;
|
reg pciw_fifo_wenable_out;
|
assign pciw_fifo_control_out[`DATA_ERROR_CTRL_BIT] = 1'b0 ;
|
assign pciw_fifo_wenable = load_to_pciw_fifo_in ;
|
assign pciw_fifo_control_out[`LAST_CTRL_BIT] = rdy_in &&
|
reg [3:0] pciw_fifo_control_out;
|
(next_write_to_pciw_fifo_is_last || last_reg_in || pciw_fifo_almost_full_in || ~addr_burst_ok || io_memory_bus_command);
|
reg [31:0] pciw_fifo_addr_data_out;
|
|
reg [3:0] pciw_fifo_cbe_out;
|
|
always@(posedge clk_in or posedge reset_in)
|
|
begin
|
|
if (reset_in)
|
|
begin
|
|
pciw_fifo_wenable_out = 1'b0;
|
|
pciw_fifo_control_out = 4'h0;
|
|
// data and address outputs assignments to PCIW_FIFO - correction of 2 LSBits
|
|
pciw_fifo_addr_data_out = 32'h0;
|
|
pciw_fifo_cbe_out = 4'h0;
|
|
end
|
|
else
|
|
begin
|
|
pciw_fifo_wenable_out = load_to_pciw_fifo_in ;
|
|
pciw_fifo_control_out[`ADDR_CTRL_BIT] = ~rdy_in ;
|
|
pciw_fifo_control_out[`BURST_BIT] = rdy_in ? ~frame_reg_in : 1'b0 ;
|
|
// if '1' then next burst BE is not equat to current one => burst will be chopped into single transfers
|
|
pciw_fifo_control_out[`DATA_ERROR_CTRL_BIT] = rdy_in && (next_be_in != be_in) && ~bckp_trdy_in; // valid comp.
|
|
pciw_fifo_control_out[`LAST_CTRL_BIT] = rdy_in && (next_write_to_pciw_fifo_is_last ||
|
|
last_reg_in || pciw_fifo_almost_full_in ||
|
|
~addr_burst_ok || io_memory_bus_command);
|
|
// data and address outputs assignments to PCIW_FIFO - correction of 2 LSBits
|
|
pciw_fifo_addr_data_out = rdy_in ? data_in : {norm_address[31:2],
|
|
norm_address[1] && io_memory_bus_command,
|
|
norm_address[0] && io_memory_bus_command} ;
|
|
pciw_fifo_cbe_out = rdy_in ? be_in : norm_bc ;
|
|
end
|
|
end
|
|
|
`ifdef HOST
|
`ifdef HOST
|
`ifdef NO_CNF_IMAGE
|
`ifdef NO_CNF_IMAGE
|
// data and address outputs assignments to PCI Target FSM
|
// data and address outputs assignments to PCI Target FSM
|
assign data_out = pcir_fifo_data ;
|
assign data_out = pcir_fifo_data ;
|
| Line 872... |
Line 909... |
assign we_out = 1'b0 ;
|
assign we_out = 1'b0 ;
|
assign bc_out = norm_bc ;
|
assign bc_out = norm_bc ;
|
// burst is OK for reads when there is ((MEM_READ_LN or MEM_READ_MUL) and AD[1:0]==2'b00) OR
|
// burst is OK for reads when there is ((MEM_READ_LN or MEM_READ_MUL) and AD[1:0]==2'b00) OR
|
// (MEM_READ and Prefetchable_IMAGE and AD[1:0]==2'b00)
|
// (MEM_READ and Prefetchable_IMAGE and AD[1:0]==2'b00)
|
assign burst_ok_out = (norm_bc[3] && addr_burst_ok) || (norm_bc[2] && norm_prf_en && addr_burst_ok) ;
|
assign burst_ok_out = (norm_bc[3] && addr_burst_ok) || (norm_bc[2] && norm_prf_en && addr_burst_ok) ;
|
// data and address outputs assignments to PCIW_FIFO - correction of 2 LSBits
|
|
assign pciw_fifo_addr_data_out = rdy_in ? data_in : {norm_address[31:2], norm_address[1] && io_memory_bus_command,
|
|
norm_address[0] && io_memory_bus_command} ;
|
|
assign pciw_fifo_cbe_out = rdy_in ? be_in : norm_bc ;
|
|
// data and address outputs assignments to Configuration space
|
// data and address outputs assignments to Configuration space
|
`ifdef HOST
|
`ifdef HOST
|
`ifdef NO_CNF_IMAGE
|
`ifdef NO_CNF_IMAGE
|
assign conf_data_out = 32'h0 ;
|
assign conf_data_out = 32'h0 ;
|
assign conf_addr_out = 12'h0 ;
|
assign conf_addr_out = 12'h0 ;
|
