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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2002/08/22 13:28:04 mihad
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// Updated for synthesis purposes. Gate level simulation was failing in some configurations
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//
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// Revision 1.4 2002/02/19 16:32:37 mihad
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// Revision 1.4 2002/02/19 16:32:37 mihad
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// Modified testbench and fixed some bugs
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// Modified testbench and fixed some bugs
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//
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//
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// Revision 1.3 2002/02/01 15:25:12 mihad
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// Revision 1.3 2002/02/01 15:25:12 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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// Repaired a few bugs, updated specification, added test bench files and design document
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Line 758... |
pcir_fifo_ctrl_reg <= #`FF_DELAY pcir_fifo_control_input ;
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pcir_fifo_ctrl_reg <= #`FF_DELAY pcir_fifo_control_input ;
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end
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end
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end
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end
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end
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end
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// when disconnect is signalled, the next data written to fifo will be the last
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// also when this happens, disconnect must stay asserted until last data is written to the fifo
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reg next_write_to_pciw_fifo_is_last ;
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// selecting "fifo data" from medium registers or from PCIR_FIFO
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// selecting "fifo data" from medium registers or from PCIR_FIFO
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wire [31:0] pcir_fifo_data = (sel_fifo_mreg_in && !pcir_fifo_empty_in) ? pcir_fifo_data_in : pcir_fifo_data_reg ;
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wire [31:0] pcir_fifo_data = (sel_fifo_mreg_in && !pcir_fifo_empty_in) ? pcir_fifo_data_in : pcir_fifo_data_reg ;
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wire [3:0] pcir_fifo_ctrl = (sel_fifo_mreg_in && !pcir_fifo_empty_in) ? pcir_fifo_control_input : pcir_fifo_ctrl_reg ;
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wire [3:0] pcir_fifo_ctrl = (sel_fifo_mreg_in && !pcir_fifo_empty_in) ? pcir_fifo_control_input : pcir_fifo_ctrl_reg ;
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// signal assignments to PCI Target FSM
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// signal assignments to PCI Target FSM
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Line 774... |
// when '1', the bus command is IO command - not supported commands are checked in pci_decoder modules
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// when '1', the bus command is IO command - not supported commands are checked in pci_decoder modules
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wire io_memory_bus_command = !norm_bc[3] && !norm_bc[2] ;
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wire io_memory_bus_command = !norm_bc[3] && !norm_bc[2] ;
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assign disconect_wo_data_out = (
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assign disconect_wo_data_out = (
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((/*pcir_fifo_ctrl[`LAST_CTRL_BIT] ||*/ pcir_fifo_empty_in || ~burst_ok_out/*addr_burst_ok*/ || io_memory_bus_command) &&
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((/*pcir_fifo_ctrl[`LAST_CTRL_BIT] ||*/ pcir_fifo_empty_in || ~burst_ok_out/*addr_burst_ok*/ || io_memory_bus_command) &&
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~bc0_in && ~frame_reg_in) ||
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~bc0_in && ~frame_reg_in) ||
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((pciw_fifo_full_in || pciw_fifo_almost_full_in || pciw_fifo_two_left_in || ~addr_burst_ok || io_memory_bus_command) &&
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((pciw_fifo_full_in || pciw_fifo_almost_full_in || next_write_to_pciw_fifo_is_last || (pciw_fifo_two_left_in && pciw_fifo_wenable_out) || ~addr_burst_ok || io_memory_bus_command) &&
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bc0_in && ~frame_reg_in)
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bc0_in && ~frame_reg_in)
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) ;
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) ;
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assign disconect_w_data_out = (
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assign disconect_w_data_out = (
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( burst_ok_out && !io_memory_bus_command && ~bc0_in ) ||
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( burst_ok_out && !io_memory_bus_command && ~bc0_in ) ||
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( addr_burst_ok && !io_memory_bus_command && bc0_in )
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( addr_burst_ok && !io_memory_bus_command && bc0_in )
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Line 821... |
.clk_in (clk_in),
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.clk_in (clk_in),
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.async_reset_data_out (pcir_fifo_flush_reg),
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.async_reset_data_out (pcir_fifo_flush_reg),
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.reset_in (reset_in)
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.reset_in (reset_in)
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) ;
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) ;
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always@(posedge clk_in or posedge reset_in)
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begin
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if (reset_in)
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next_write_to_pciw_fifo_is_last <= #1 1'b0 ;
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else if (next_write_to_pciw_fifo_is_last && pciw_fifo_wenable_out)
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next_write_to_pciw_fifo_is_last <= #1 1'b0 ;
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else if (pciw_fifo_wenable_out && disconect_wo_data_out)
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next_write_to_pciw_fifo_is_last <= #1 1'b1 ;
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end
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// signal assignments from fifo to PCI Target FSM
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// signal assignments from fifo to PCI Target FSM
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assign wbw_fifo_empty_out = wbw_fifo_empty_in ;
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assign wbw_fifo_empty_out = wbw_fifo_empty_in ;
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assign wbu_del_read_comp_pending_out = wbu_del_read_comp_pending_in ;
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assign wbu_del_read_comp_pending_out = wbu_del_read_comp_pending_in ;
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assign pciw_fifo_full_out = (pciw_fifo_full_in || pciw_fifo_almost_full_in || pciw_fifo_two_left_in) ;
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assign pciw_fifo_full_out = (pciw_fifo_full_in || pciw_fifo_almost_full_in || pciw_fifo_two_left_in) ;
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assign pcir_fifo_data_err_out = pcir_fifo_ctrl[`DATA_ERROR_CTRL_BIT] && !sel_conf_fifo_in ;
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assign pcir_fifo_data_err_out = pcir_fifo_ctrl[`DATA_ERROR_CTRL_BIT] && !sel_conf_fifo_in ;
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Line 843... |
assign pcir_fifo_renable_out = fetch_pcir_fifo_in && !pcir_fifo_empty_in ;
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assign pcir_fifo_renable_out = fetch_pcir_fifo_in && !pcir_fifo_empty_in ;
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assign pciw_fifo_wenable_out = load_to_pciw_fifo_in ;
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assign pciw_fifo_wenable_out = load_to_pciw_fifo_in ;
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assign pciw_fifo_control_out[`ADDR_CTRL_BIT] = ~rdy_in ;
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assign pciw_fifo_control_out[`ADDR_CTRL_BIT] = ~rdy_in ;
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assign pciw_fifo_control_out[`BURST_BIT] = rdy_in ? ~frame_reg_in : 1'b0 ;
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assign pciw_fifo_control_out[`BURST_BIT] = rdy_in ? ~frame_reg_in : 1'b0 ;
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assign pciw_fifo_control_out[`DATA_ERROR_CTRL_BIT] = 1'b0 ;
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assign pciw_fifo_control_out[`DATA_ERROR_CTRL_BIT] = 1'b0 ;
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assign pciw_fifo_control_out[`LAST_CTRL_BIT] = rdy_in ?
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assign pciw_fifo_control_out[`LAST_CTRL_BIT] = rdy_in &&
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(last_reg_in || pciw_fifo_almost_full_in || ~addr_burst_ok || io_memory_bus_command) : 1'b0 ;
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(next_write_to_pciw_fifo_is_last || last_reg_in || pciw_fifo_almost_full_in || ~addr_burst_ok || io_memory_bus_command);
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`ifdef HOST
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`ifdef HOST
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`ifdef NO_CNF_IMAGE
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`ifdef NO_CNF_IMAGE
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// data and address outputs assignments to PCI Target FSM
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// data and address outputs assignments to PCI Target FSM
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assign data_out = pcir_fifo_data ;
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assign data_out = pcir_fifo_data ;
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