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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2002/02/01 14:43:31 mihad
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// *** empty log message ***
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//
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//
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//
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// Fifo implementation defines:
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// Fifo implementation defines:
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// If FPGA and XILINX are defined, Xilinx's BlockSelectRAM+ is instantiated for Fifo storage.
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// If FPGA and XILINX are defined, Xilinx's BlockSelectRAM+ is instantiated for Fifo storage.
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// 16 bit width is used, so 8 bits of address ( 256 ) locations are available. If RAM_DONT_SHARE is not defined (commented out),
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// 16 bit width is used, so 8 bits of address ( 256 ) locations are available. If RAM_DONT_SHARE is not defined (commented out),
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Line 55... |
// If RAM_DONT_SHARE is defined, then all RAM address lengths must be specified accordingly, otherwise there are two relevant lengths - PCI_FIFO_RAM_ADDR_LENGTH and
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// If RAM_DONT_SHARE is defined, then all RAM address lengths must be specified accordingly, otherwise there are two relevant lengths - PCI_FIFO_RAM_ADDR_LENGTH and
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// WB_FIFO_RAM_ADDR_LENGTH.
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// WB_FIFO_RAM_ADDR_LENGTH.
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`define WBW_ADDR_LENGTH 6
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`define WBW_ADDR_LENGTH 6
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`define WBR_ADDR_LENGTH 4
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`define WBR_ADDR_LENGTH 4
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`define PCIW_ADDR_LENGTH 6
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`define PCIW_ADDR_LENGTH 3
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`define PCIR_ADDR_LENGTH 3
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`define PCIR_ADDR_LENGTH 3
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`define FPGA
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//`define FPGA
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`define XILINX
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//`define XILINX
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//`define WB_RAM_DONT_SHARE
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//`define WB_RAM_DONT_SHARE
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//`define PCI_RAM_DONT_SHARE
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//`define PCI_RAM_DONT_SHARE
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`ifdef FPGA
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`ifdef FPGA
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`define WB_XILINX_RAMB4
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`define WB_XILINX_RAMB4
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//`define PCI_XILINX_DIST_RAM
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//`define PCI_XILINX_DIST_RAM
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//`define WB_XILINX_DIST_RAM
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//`define WB_XILINX_DIST_RAM
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`endif
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`endif
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`else
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`else
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`define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
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`define PCI_FIFO_RAM_ADDR_LENGTH 4 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
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`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
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`define WB_FIFO_RAM_ADDR_LENGTH 7 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
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`define WB_ARTISAN_SDP
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// `define WB_ARTISAN_SDP
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`define PCI_ARTISAN_SDP
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// `define PCI_ARTISAN_SDP
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`endif
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`endif
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// these two defines allow user to select active high or low output enables on PCI bus signals, depending on
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// these two defines allow user to select active high or low output enables on PCI bus signals, depending on
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// output buffers instantiated. Xilinx FPGAs use active low output enables.
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// output buffers instantiated. Xilinx FPGAs use active low output enables.
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`define ACTIVE_LOW_OE
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`define ACTIVE_LOW_OE
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`define WB_CONFIGURATION_BASE 20'h0000_0
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`define WB_CONFIGURATION_BASE 20'h0000_0
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// Turn registered WISHBONE slave outputs on or off
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// Turn registered WISHBONE slave outputs on or off
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// all outputs from WB Slave state machine are registered, if this is defined - WB bus outputs as well as
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// all outputs from WB Slave state machine are registered, if this is defined - WB bus outputs as well as
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// outputs to internals of the core.
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// outputs to internals of the core.
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`define REGISTER_WBS_OUTPUTS
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//`define REGISTER_WBS_OUTPUTS
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/*-----------------------------------------------------------------------------------------------------------
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/*-----------------------------------------------------------------------------------------------------------
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Core speed definition - used for simulation and 66MHz Capable bit value in status register indicating 66MHz
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Core speed definition - used for simulation and 66MHz Capable bit value in status register indicating 66MHz
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capable device
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capable device
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-----------------------------------------------------------------------------------------------------------*/
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-----------------------------------------------------------------------------------------------------------*/
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Line 202... |
`define HEADER_REVISION_ID 8'h01
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`define HEADER_REVISION_ID 8'h01
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// Turn registered WISHBONE master outputs on or off
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// Turn registered WISHBONE master outputs on or off
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// all outputs from WB Master state machine are registered, if this is defined - WB bus outputs as well as
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// all outputs from WB Master state machine are registered, if this is defined - WB bus outputs as well as
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// outputs to internals of the core.
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// outputs to internals of the core.
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//`define REGISTER_WBM_OUTPUTS
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`define REGISTER_WBM_OUTPUTS
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// MAX Retry counter value for WISHBONE Master state-machine
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// MAX Retry counter value for WISHBONE Master state-machine
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// This value is 8-bit because of 8-bit retry counter !!!
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// This value is 8-bit because of 8-bit retry counter !!!
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`define WB_RTY_CNT_MAX 8'hff
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`define WB_RTY_CNT_MAX 8'hff
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No newline at end of file
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No newline at end of file
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