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Line 40... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2003/01/27 16:49:31 mihad
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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//
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// Revision 1.6 2002/11/27 20:36:12 mihad
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// Revision 1.6 2002/11/27 20:36:12 mihad
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// Changed the code a bit to make it more readable.
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// Changed the code a bit to make it more readable.
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// Functionality not changed in any way.
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// Functionality not changed in any way.
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// More robust synchronization in fifos is still pending.
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// More robust synchronization in fifos is still pending.
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//
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//
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Gray coded write address pointer is synchronized to read clock domain and compared to Gray coded read address pointer.
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Gray coded write address pointer is synchronized to read clock domain and compared to Gray coded read address pointer.
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If they are equal, fifo is empty.
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If they are equal, fifo is empty.
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--------------------------------------------------------------------------------------------------------------------------------*/
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--------------------------------------------------------------------------------------------------------------------------------*/
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wire [(ADDR_LENGTH - 1):0] rclk_sync_wgrey_addr ;
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wire [(ADDR_LENGTH - 1):0] rclk_sync_wgrey_addr ;
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reg [(ADDR_LENGTH - 1):0] rclk_wgrey_addr ;
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reg [(ADDR_LENGTH - 1):0] rclk_wgrey_addr ;
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synchronizer_flop #(ADDR_LENGTH) i_synchronizer_reg_wgrey_addr
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synchronizer_flop #(ADDR_LENGTH, 0) i_synchronizer_reg_wgrey_addr
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(
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(
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.data_in (wgrey_addr),
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.data_in (wgrey_addr),
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.clk_out (rclock_in),
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.clk_out (rclock_in),
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.sync_data_out (rclk_sync_wgrey_addr),
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.sync_data_out (rclk_sync_wgrey_addr),
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.async_reset (1'b0)
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.async_reset (clear)
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) ;
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) ;
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always@(posedge rclock_in)
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always@(posedge rclock_in or posedge clear)
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begin
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begin
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if (clear)
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rclk_wgrey_addr <= #`FF_DELAY 0 ;
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else
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rclk_wgrey_addr <= #`FF_DELAY rclk_sync_wgrey_addr ;
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rclk_wgrey_addr <= #`FF_DELAY rclk_sync_wgrey_addr ;
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end
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end
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assign empty = (rgrey_addr == rclk_wgrey_addr) ;
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assign empty = (rgrey_addr == rclk_wgrey_addr) ;
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endmodule
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endmodule
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