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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2003/01/27 16:49:31 mihad
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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//
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// Revision 1.9 2002/10/18 03:36:37 tadejm
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// Revision 1.9 2002/10/18 03:36:37 tadejm
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// Changed wrong signal name scanb_sen into scanb_en.
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// Changed wrong signal name scanb_sen into scanb_en.
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//
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//
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// Revision 1.8 2002/10/17 22:49:22 tadejm
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// Revision 1.8 2002/10/17 22:49:22 tadejm
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// Changed BIST signals for RAMs.
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// Changed BIST signals for RAMs.
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Line 532... |
else
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else
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if (in_count_en)
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if (in_count_en)
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inGreyCount <= #`FF_DELAY inNextGreyCount ;
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inGreyCount <= #`FF_DELAY inNextGreyCount ;
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end
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end
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wire [(WBW_ADDR_LENGTH-2):0] pci_clk_sync_inGreyCount ;
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reg [(WBW_ADDR_LENGTH-2):0] pci_clk_inGreyCount ;
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synchronizer_flop #((WBW_ADDR_LENGTH - 1)) i_synchronizer_reg_inGreyCount
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(
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.data_in (inGreyCount),
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.clk_out (pci_clock_in),
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.sync_data_out (pci_clk_sync_inGreyCount),
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.async_reset (1'b0)
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) ;
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always@(posedge pci_clock_in or posedge wbw_clear)
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begin
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if (wbw_clear)
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pci_clk_inGreyCount <= #`FF_DELAY 1 ;
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else
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pci_clk_inGreyCount <= # `FF_DELAY pci_clk_sync_inGreyCount ;
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end
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// register holding grey coded count of outgoing transactions
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// register holding grey coded count of outgoing transactions
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always@(posedge pci_clock_in or posedge wbw_clear)
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always@(posedge pci_clock_in or posedge wbw_clear)
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begin
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begin
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if (wbw_clear)
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if (wbw_clear)
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begin
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begin
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Line 583... |
else
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else
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if (out_count_en)
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if (out_count_en)
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wbw_outTransactionCount <= #`FF_DELAY wbw_outTransactionCount + 1'b1 ;
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wbw_outTransactionCount <= #`FF_DELAY wbw_outTransactionCount + 1'b1 ;
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end
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end
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// synchronize transaction ready output to reading clock
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assign wbw_transaction_ready_out = pci_clk_inGreyCount != outGreyCount ;
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// transaction ready is set when incoming transaction count is not equal to outgoing transaction count (what goes in must come out logic)
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// transaction ready is cleared when whole transaction is pulled out of fifo (otherwise it could stay set for additional cycle and result in wrong op.)
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wire wbw_transaction_ready_flop_i = inGreyCount != outGreyCount ;
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meta_flop #(0) i_meta_flop_wbw_transaction_ready
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(
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.rst_i (wbw_clear),
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.clk_i (pci_clock_in),
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.ld_i (out_count_en),
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.ld_val_i (1'b0),
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.en_i (1'b1),
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.d_i (wbw_transaction_ready_flop_i),
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.meta_q_o (wbw_transaction_ready_out)
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) ;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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