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Line 40... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2003/01/30 22:01:09 mihad
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// Updated synchronization in top level fifo modules.
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//
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// Revision 1.1 2003/01/27 16:49:31 mihad
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// Revision 1.1 2003/01/27 16:49:31 mihad
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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//
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//
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// Revision 1.9 2002/10/18 03:36:37 tadejm
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// Revision 1.9 2002/10/18 03:36:37 tadejm
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// Changed wrong signal name scanb_sen into scanb_en.
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// Changed wrong signal name scanb_sen into scanb_en.
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Line 527... |
// register holding grey coded count of incoming transactions
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// register holding grey coded count of incoming transactions
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always@(posedge wb_clock_in or posedge wbw_clear)
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always@(posedge wb_clock_in or posedge wbw_clear)
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begin
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begin
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if (wbw_clear)
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if (wbw_clear)
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begin
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begin
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inGreyCount[(WBW_ADDR_LENGTH-2)] <= #`FF_DELAY 1'b1 ;
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inGreyCount <= #`FF_DELAY 0 ;
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inGreyCount[(WBW_ADDR_LENGTH-3):0] <= #`FF_DELAY {(WBW_ADDR_LENGTH-2),1'b0} ;
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end
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end
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else
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else
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if (in_count_en)
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if (in_count_en)
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inGreyCount <= #`FF_DELAY inNextGreyCount ;
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inGreyCount <= #`FF_DELAY inNextGreyCount ;
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end
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end
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wire [(WBW_ADDR_LENGTH-2):0] pci_clk_sync_inGreyCount ;
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wire [(WBW_ADDR_LENGTH-2):0] pci_clk_sync_inGreyCount ;
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reg [(WBW_ADDR_LENGTH-2):0] pci_clk_inGreyCount ;
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reg [(WBW_ADDR_LENGTH-2):0] pci_clk_inGreyCount ;
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synchronizer_flop #((WBW_ADDR_LENGTH - 1)) i_synchronizer_reg_inGreyCount
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synchronizer_flop #((WBW_ADDR_LENGTH - 1), 0) i_synchronizer_reg_inGreyCount
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(
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(
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.data_in (inGreyCount),
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.data_in (inGreyCount),
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.clk_out (pci_clock_in),
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.clk_out (pci_clock_in),
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.sync_data_out (pci_clk_sync_inGreyCount),
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.sync_data_out (pci_clk_sync_inGreyCount),
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.async_reset (1'b0)
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.async_reset (wbw_clear)
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) ;
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) ;
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always@(posedge pci_clock_in or posedge wbw_clear)
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always@(posedge pci_clock_in or posedge wbw_clear)
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begin
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begin
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if (wbw_clear)
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if (wbw_clear)
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pci_clk_inGreyCount <= #`FF_DELAY 1 ;
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pci_clk_inGreyCount <= #`FF_DELAY 0 ;
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else
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else
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pci_clk_inGreyCount <= # `FF_DELAY pci_clk_sync_inGreyCount ;
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pci_clk_inGreyCount <= # `FF_DELAY pci_clk_sync_inGreyCount ;
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end
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end
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// register holding grey coded count of outgoing transactions
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// register holding grey coded count of outgoing transactions
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always@(posedge pci_clock_in or posedge wbw_clear)
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always@(posedge pci_clock_in or posedge wbw_clear)
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begin
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begin
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if (wbw_clear)
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if (wbw_clear)
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begin
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begin
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outGreyCount[(WBW_ADDR_LENGTH-2)] <= #`FF_DELAY 1'b1 ;
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outGreyCount <= #`FF_DELAY 0 ;
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outGreyCount[(WBW_ADDR_LENGTH-3):0] <= #`FF_DELAY {(WBW_ADDR_LENGTH-2),1'b0} ;
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end
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end
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else
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else
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if (out_count_en)
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if (out_count_en)
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outGreyCount <= #`FF_DELAY outNextGreyCount ;
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outGreyCount <= #`FF_DELAY outNextGreyCount ;
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end
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end
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// incoming transactions counter
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// incoming transactions counter
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always@(posedge wb_clock_in or posedge wbw_clear)
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always@(posedge wb_clock_in or posedge wbw_clear)
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begin
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begin
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if (wbw_clear)
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if (wbw_clear)
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wbw_inTransactionCount <= #`FF_DELAY {(WBW_ADDR_LENGTH-1){1'b0}} ;
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wbw_inTransactionCount <= #`FF_DELAY 1 ;
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else
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else
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if (in_count_en)
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if (in_count_en)
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wbw_inTransactionCount <= #`FF_DELAY wbw_inTransactionCount + 1'b1 ;
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wbw_inTransactionCount <= #`FF_DELAY wbw_inTransactionCount + 1'b1 ;
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end
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end
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// outgoing transactions counter
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// outgoing transactions counter
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always@(posedge pci_clock_in or posedge wbw_clear)
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always@(posedge pci_clock_in or posedge wbw_clear)
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begin
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begin
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if (wbw_clear)
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if (wbw_clear)
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wbw_outTransactionCount <= #`FF_DELAY {(WBW_ADDR_LENGTH-1){1'b0}} ;
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wbw_outTransactionCount <= 1 ;
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else
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else
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if (out_count_en)
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if (out_count_en)
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wbw_outTransactionCount <= #`FF_DELAY wbw_outTransactionCount + 1'b1 ;
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wbw_outTransactionCount <= #`FF_DELAY wbw_outTransactionCount + 1'b1 ;
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end
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end
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