| Line 29... |
Line 29... |
set arg_regression = 0;
|
set arg_regression = 0;
|
set arg_xilinx = 0;
|
set arg_xilinx = 0;
|
set arg_artisan = 0;
|
set arg_artisan = 0;
|
set arg_waves = 0;
|
set arg_waves = 0;
|
set arg_vs_hdtp = 0
|
set arg_vs_hdtp = 0
|
|
set arg_dis_comp_exp_test = 0
|
|
|
@ arg_num = 1
|
@ arg_num = 1
|
set arg_check = 0
|
set arg_check = 0
|
|
|
while($arg_num <= $#argv)
|
while($arg_num <= $#argv)
|
|
if ($argv[$arg_num] == "help") then
|
|
goto help
|
|
endif
|
|
|
if ($argv[$arg_num] == "regression") then
|
if ($argv[$arg_num] == "regression") then
|
@ arg_regression = 1
|
@ arg_regression = 1
|
@ arg_check = $arg_check + 1
|
@ arg_check = $arg_check + 1
|
endif
|
endif
|
|
|
| Line 59... |
Line 64... |
if ($argv[$arg_num] == "vs_two_port") then
|
if ($argv[$arg_num] == "vs_two_port") then
|
@ arg_vs_hdtp = 1
|
@ arg_vs_hdtp = 1
|
@ arg_check = $arg_check + 1
|
@ arg_check = $arg_check + 1
|
endif
|
endif
|
|
|
|
if ($argv[$arg_num] == "disable_completion_expired_tests") then
|
|
@ arg_dis_comp_exp_test = 1
|
|
@ arg_check = $arg_check + 1
|
|
endif
|
|
|
if ($arg_check != $arg_num) then
|
if ($arg_check != $arg_num) then
|
echo "Invalid argument found"
|
echo "Invalid argument found: $argv[$arg_num]"
|
exit
|
echo
|
|
goto help
|
endif
|
endif
|
@ arg_num = $arg_num + 1
|
@ arg_num = $arg_num + 1
|
end
|
end
|
|
|
# ITERATION LOOP
|
# ITERATION LOOP
|
| Line 168... |
Line 179... |
echo "\tGUEST, REGR_FIFO_LARGE_GENERIC, WB_DECODE_MEDIUM, PCI_DECODE_MAX, "
|
echo "\tGUEST, REGR_FIFO_LARGE_GENERIC, WB_DECODE_MEDIUM, PCI_DECODE_MAX, "
|
echo "\tWB_DECODE_MED, PCI33, WB_CLK10, ACTIVE_HIGH_OE, WB_CNF_BASE_ZERO, "
|
echo "\tWB_DECODE_MED, PCI33, WB_CLK10, ACTIVE_HIGH_OE, WB_CNF_BASE_ZERO, "
|
echo "\tNO_CNF_IMAGE, WB_IMAGE2, WB_IMAGE3, WB_IMAGE4, WB_IMAGE5. "
|
echo "\tNO_CNF_IMAGE, WB_IMAGE2, WB_IMAGE3, WB_IMAGE4, WB_IMAGE5. "
|
echo "-DEFINE REGRESSION -DEFINE GUEST -DEFINE REGR_FIFO_LARGE_GENERIC -DEFINE WB_DECODE_MEDIUM -DEFINE PCI_DECODE_MAX -DEFINE WB_DECODE_MED -DEFINE PCI33 -DEFINE WB_CLK10 -DEFINE ACTIVE_HIGH_OE -DEFINE WB_CNF_BASE_ZERO -DEFINE NO_CNF_IMAGE -DEFINE WB_IMAGE2 -DEFINE WB_IMAGE3 -DEFINE WB_IMAGE4 -DEFINE WB_IMAGE5" > ./defines.args
|
echo "-DEFINE REGRESSION -DEFINE GUEST -DEFINE REGR_FIFO_LARGE_GENERIC -DEFINE WB_DECODE_MEDIUM -DEFINE PCI_DECODE_MAX -DEFINE WB_DECODE_MED -DEFINE PCI33 -DEFINE WB_CLK10 -DEFINE ACTIVE_HIGH_OE -DEFINE WB_CNF_BASE_ZERO -DEFINE NO_CNF_IMAGE -DEFINE WB_IMAGE2 -DEFINE WB_IMAGE3 -DEFINE WB_IMAGE4 -DEFINE WB_IMAGE5" > ./defines.args
|
endif
|
endif
|
|
|
|
if ($arg_dis_comp_exp_test) then
|
|
echo "-DEFINE DISABLE_COMPLETION_EXPIRED_TESTS" >> ./defines.args
|
|
endif
|
else
|
else
|
if (($arg_xilinx == 0) && ($arg_artisan == 1)) then
|
if (($arg_xilinx == 0) && ($arg_artisan == 1)) then
|
if ($iter == 1) then
|
if ($iter == 1) then
|
echo "<<< Defines:"
|
echo "<<< Defines:"
|
echo "\tHOST, REGR_FIFO_SMALL_GENERIC, WB_DECODE_FAST, PCI_DECODE_MAX, "
|
echo "\tHOST, REGR_FIFO_SMALL_GENERIC, WB_DECODE_FAST, PCI_DECODE_MAX, "
|
| Line 582... |
Line 597... |
echo "<<< ../log/*pciu_mon.log "
|
echo "<<< ../log/*pciu_mon.log "
|
echo "<<< ../log/*wbu_mon.log "
|
echo "<<< ../log/*wbu_mon.log "
|
echo "<<< ../log/*ncsim.log "
|
echo "<<< ../log/*ncsim.log "
|
echo "<<<"
|
echo "<<<"
|
endif
|
endif
|
|
exit
|
|
|
|
help:
|
|
echo ""
|
|
echo "Script arguments:"
|
|
echo ""
|
|
echo "regression : run all implemented regression iterations on PCI Bridge Design"
|
|
echo ""
|
|
echo "xilinx : if you want to run simulation with xilinx RAM primitives. You have to provide RAM16X1D.v, RAMB4_S16_S16.v and glbl.v simulation files."
|
|
echo " : you have to edit ../bin/xilinx_file_list.lst file with the correct paths to these files. Leave other paths as they are!"
|
|
echo ""
|
|
echo "artisan : if you want to run simulation with artisan ASIC library vendor RAM primitives. You have to provide simulation models for these, edit ../bin/artisan_file_list.lst,"
|
|
echo " : and optionaly ../../../rtl/verilog/pci_user_constants.v, ../../../bench/verilog/pci_regression_constants.v, ../../../rtl/verilog/wb_tpram.v and ../../../rtl/verilog/pci_tpram.v"
|
|
echo ""
|
|
echo "waves : if you want to dump all the signals in the testbench to the signalscan output file in ../out/ directory"
|
|
echo ""
|
|
echo "vs_two_port : if you want to run simulation with virtual silicon ASIC library vendor RAM primitives. You have to provide simulation models for these, edit ../bin/vs_file_list.lst,"
|
|
echo " : and optionaly ../../../rtl/verilog/pci_user_constants.v, ../../../bench/verilog/pci_regression_constants.v, ../../../rtl/verilog/wb_tpram.v and ../../../rtl/verilog/pci_tpram.v"
|
|
echo ""
|
|
echo "disable_completion_expired_tests : if you want to disable completion expiration testing during regression run, because these are time consuming tests"
|
|
echo ""
|
|
exit
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
