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//===========================================================================
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//===========================================================================
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// $Id: pci_bus_monitor.v,v 1.3 2002-08-13 11:03:51 mihad Exp $
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// $Id: pci_bus_monitor.v,v 1.4 2003-08-03 18:04:44 mihad Exp $
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//
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//
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// Copyright 2001 Blue Beaver. All Rights Reserved.
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// Copyright 2001 Blue Beaver. All Rights Reserved.
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//
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//
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// Summary: Watch the PCI Bus Wires to try to see Protocol Errors.
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// Summary: Watch the PCI Bus Wires to try to see Protocol Errors.
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// This module also has access to the individual PCI Bus OE
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// This module also has access to the individual PCI Bus OE
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end
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end
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`NO_ELSE;
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`NO_ELSE;
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end
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end
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wire [4:0] grant_now = {pci_ext_gnt_l[3:0], pci_real_gnt_l} ;
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always @(posedge pci_ext_clk or negedge pci_ext_reset_l)
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always @(posedge pci_ext_clk or negedge pci_ext_reset_l)
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begin
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begin
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if (pci_ext_reset_l == 1'b0)
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if (pci_ext_reset_l == 1'b0)
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begin
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begin
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grant_prev <= 5'h00;
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grant_prev <= 5'h00;
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address_phase_prev <= 1'b0;
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address_phase_prev <= 1'b0;
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read_operation_prev <= 1'b0;
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read_operation_prev <= 1'b0;
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end
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end
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else
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else
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begin
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begin
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grant_prev <= {pci_ext_gnt_l[3:0], pci_real_gnt_l};
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grant_prev <= grant_now ;
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ad_prev[PCI_BUS_DATA_RANGE:0] <= pci_ext_ad[PCI_BUS_DATA_RANGE:0];
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ad_prev[PCI_BUS_DATA_RANGE:0] <= pci_ext_ad[PCI_BUS_DATA_RANGE:0];
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cbe_l_prev[PCI_BUS_CBE_RANGE:0] <= pci_ext_cbe_l[PCI_BUS_CBE_RANGE:0];
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cbe_l_prev[PCI_BUS_CBE_RANGE:0] <= pci_ext_cbe_l[PCI_BUS_CBE_RANGE:0];
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frame_prev <= frame_now;
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frame_prev <= frame_now;
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irdy_prev <= irdy_now;
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irdy_prev <= irdy_now;
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devsel_prev <= devsel_now;
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devsel_prev <= devsel_now;
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ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
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ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
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default:
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default:
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begin
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begin
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$display ("*** monitor - Unknown operation started, AD: 'h%x, CBE: 'h%x, at time %t",
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$display ("*** monitor - Unknown operation started, AD: 'h%x, CBE: 'h%x, at time %t",
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ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
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ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
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$fdisplay (log_file_desc,
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error_detected <= ~error_detected;
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error_detected <= ~error_detected;
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end
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end
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endcase
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endcase
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end
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end
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`NO_ELSE;
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`NO_ELSE;
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end
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end
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`endif // VERBOSE_MONITOR_DEVICE
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`endif // VERBOSE_MONITOR_DEVICE
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endmodule
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initial get_pci_op.timeout_val = 32'hffff ;
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reg [4:0] cur_transaction_owner ;
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initial cur_transaction_owner = 5'h1F ;
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task get_pci_op ;
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output [31:0] address_o ;
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output [3:0 ] bus_command_o ;
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reg [31:0] timeout_val ;
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reg in_use ;
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begin:main
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if (in_use === 1'b1)
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begin
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$display("%m re-entered!") ;
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$fdisplay(log_file_desc, "%m re-entered!") ;
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error_detected <= ~error_detected;
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disable main ;
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end
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in_use = 1'b1 ;
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fork
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begin:get_op_blk
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wait(pci_ext_reset_l === 1'b1) ;
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@(posedge pci_ext_clk) ;
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while ((frame_now !== 1'b1) | (frame_prev !== 1'b0) )
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@(posedge pci_ext_clk) ;
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disable timeout_blk ;
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address_o = pci_ext_ad ;
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bus_command_o = pci_ext_cbe_l ;
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cur_transaction_owner = grant_now ;
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end
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begin:timeout_blk
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#(timeout_val) ;
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disable get_op_blk ;
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address_o = 32'hxxxx_xxxx ;
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bus_command_o = 4'hx ;
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end
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join
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in_use = 1'b0 ;
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end
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endtask // get_pci_op
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task get_pci_op_num_of_transfers ;
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output [31:0] num_of_transfers_o ;
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output gnt_deasserted_o ;
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reg [7:0] num_of_cycles_without_transfer ;
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reg in_use ;
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begin:main
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if (in_use === 1'b1)
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begin
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$display("%m re-entered!") ;
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$fdisplay(log_file_desc, "%m re-entered!") ;
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error_detected <= ~error_detected;
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disable main ;
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end
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in_use = 1'b1 ;
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num_of_transfers_o = 0 ;
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num_of_cycles_without_transfer = 0 ;
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@(posedge pci_ext_clk) ;
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while( (frame_now === 1'b1) & (num_of_cycles_without_transfer < 128) )
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begin
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if ( (irdy_now === 1'b1) & (trdy_now === 1'b1) & (devsel_now === 1'b1))
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begin
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num_of_transfers_o = num_of_transfers_o + 1'b1 ;
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num_of_cycles_without_transfer = 0 ;
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end
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else
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begin
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num_of_cycles_without_transfer = num_of_cycles_without_transfer + 1'b1 ;
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end
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@(posedge pci_ext_clk) ;
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end
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if (num_of_cycles_without_transfer === 128)
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begin
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$display("%m, no transfers in 128 pci clock cycles! Terminating!") ;
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$fdisplay(log_file_desc, "%m, no transfers in 128 pci clock cycles! Terminating!") ;
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error_detected <= ~error_detected ;
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num_of_transfers_o = 32'hxxxx_xxxx ;
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gnt_deasserted_o = 1'bx ;
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end
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else
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begin
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gnt_deasserted_o = ( cur_transaction_owner != grant_now ) ;
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while ( (irdy_now === 1'b1) & (trdy_now === 1'b0) & (stop_now === 1'b0) )
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@(posedge pci_ext_clk) ;
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if ( (irdy_now === 1'b1) & (trdy_now === 1'b1) & (devsel_now === 1'b1))
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num_of_transfers_o = num_of_transfers_o + 1'b1 ;
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end
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in_use = 1'b0 ;
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end
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endtask // get_pci_op_num_of_transfers
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task get_pci_op_num_of_cycles ;
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output [31:0] frame_asserted_cycles_o ;
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reg [31:0] num_of_cycles_after_last_data_phase_termination ;
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reg in_use ;
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begin:main
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if (in_use === 1'b1)
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begin
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$display("%m re-entered!") ;
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$fdisplay(log_file_desc, "%m re-entered!") ;
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error_detected <= ~error_detected;
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disable main ;
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end
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in_use = 1'b1 ;
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frame_asserted_cycles_o = 1 ;
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num_of_cycles_after_last_data_phase_termination = 1 ;
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@(posedge pci_ext_clk) ;
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while( (frame_now === 1'b1) & (num_of_cycles_after_last_data_phase_termination < 128) )
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begin
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if (irdy_prev & trdy_prev & devsel_prev )
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begin
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frame_asserted_cycles_o = frame_asserted_cycles_o + num_of_cycles_after_last_data_phase_termination ;
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num_of_cycles_after_last_data_phase_termination = 1 ;
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end
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else
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num_of_cycles_after_last_data_phase_termination = num_of_cycles_after_last_data_phase_termination + 1'b1 ;
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@(posedge pci_ext_clk) ;
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end
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if ( num_of_cycles_after_last_data_phase_termination === 128)
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begin
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$display("%m, no transfers in 128 pci clock cycles! Terminating!") ;
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$fdisplay(log_file_desc, "%m, no transfers in 128 pci clock cycles! Terminating!") ;
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error_detected <= ~error_detected ;
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frame_asserted_cycles_o = 32'hxxxx_xxxx ;
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end
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in_use = 1'b0 ;
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end
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endtask // get_pci_op_num_of_cycles
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task get_pci_master_abort ;
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output [31:0 ] ret_adr_o ;
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output [ 3:0 ] ret_bc_o ;
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output ret_mabort_detected_o ;
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begin:main
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ret_mabort_detected_o = 1'b0 ;
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get_pci_op(ret_adr_o, ret_bc_o) ;
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if ( (ret_adr_o ^ ret_adr_o) !== 0 )
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disable main ;
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if ( (ret_bc_o ^ ret_bc_o) !== 0 )
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disable main ;
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while (frame_now !== 1'b0)
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begin
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if (devsel_now !== 1'b0)
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begin
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// exit immediately on target response detection
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ret_mabort_detected_o = 1'b0 ;
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disable main ;
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end
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@(posedge pci_ext_clk) ;
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end
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while(irdy_now !== 1'b0)
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begin
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if (devsel_now !== 1'b0)
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begin
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// exit immediately on target response detection
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ret_mabort_detected_o = 1'b0 ;
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disable main ;
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end
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@(posedge pci_ext_clk) ;
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end
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ret_mabort_detected_o = 1'b1 ;
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end
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endtask // get_pci_master_abort
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endmodule
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