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[/] [pci/] [tags/] [rel_7/] [bench/] [verilog/] [pci_bus_monitor.v] - Diff between revs 35 and 45
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Rev 45 |
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//===========================================================================
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//===========================================================================
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// $Id: pci_bus_monitor.v,v 1.2 2002-03-21 07:35:50 mihad Exp $
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// $Id: pci_bus_monitor.v,v 1.3 2002-08-13 11:03:51 mihad Exp $
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//
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//
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// Copyright 2001 Blue Beaver. All Rights Reserved.
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// Copyright 2001 Blue Beaver. All Rights Reserved.
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//
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//
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// Summary: Watch the PCI Bus Wires to try to see Protocol Errors.
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// Summary: Watch the PCI Bus Wires to try to see Protocol Errors.
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// This module also has access to the individual PCI Bus OE
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// This module also has access to the individual PCI Bus OE
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Line 664... |
devsel_prev <= devsel_now;
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devsel_prev <= devsel_now;
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trdy_prev <= trdy_now;
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trdy_prev <= trdy_now;
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stop_prev <= stop_now;
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stop_prev <= stop_now;
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perr_prev <= perr_now ;
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perr_prev <= perr_now ;
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if (frame_now & ~frame_prev
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if (frame_now & ~frame_prev)
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&& (pci_ext_cbe_l[PCI_BUS_CBE_RANGE:0] != PCI_COMMAND_DUAL_ADDRESS_CYCLE))
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begin
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address_phase_prev <= 1'b1;
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read_operation_prev <= ~pci_ext_cbe_l[0]; // reads have LSB == 0;
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end
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else if(address_phase_prev && (cbe_l_prev[PCI_BUS_CBE_RANGE:0] == PCI_COMMAND_DUAL_ADDRESS_CYCLE))
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begin
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begin
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address_phase_prev <= 1'b1;
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address_phase_prev <= 1'b1;
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read_operation_prev <= ~pci_ext_cbe_l[0]; // reads have LSB == 0;
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read_operation_prev <= ~pci_ext_cbe_l[0]; // reads have LSB == 0;
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end
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end
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else
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else
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