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[/] [pci/] [tags/] [rel_7/] [bench/] [verilog/] [pci_testbench_defines.v] - Diff between revs 104 and 106
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| Rev 104 |
Rev 106 |
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Line 77... |
// setup and hold time definitions for WISHBONE - used in BFMs for signal generation
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// setup and hold time definitions for WISHBONE - used in BFMs for signal generation
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`define Tsetup 3
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`define Tsetup 3
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`define Thold 1
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`define Thold 1
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// how many clock cycles should model wait for design's response - integer 32 bit value
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// how many clock cycles should model wait for design's response - integer 32 bit value
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`define WAIT_FOR_RESPONSE 6
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`define WAIT_FOR_RESPONSE 10
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// maximum number of transactions allowed in single call to block or cab transfer routines
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// maximum number of transactions allowed in single call to block or cab transfer routines
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`define MAX_BLK_SIZE 4096
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`define MAX_BLK_SIZE 4096
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// maximum retry terminations allows for WISHBONE master to repeat an access
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// maximum retry terminations allows for WISHBONE master to repeat an access
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Line 90... |
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// some common types and defines
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// some common types and defines
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`define WB_ADDR_WIDTH 32
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`define WB_ADDR_WIDTH 32
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`define WB_DATA_WIDTH 32
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`define WB_DATA_WIDTH 32
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`define WB_SEL_WIDTH `WB_DATA_WIDTH/8
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`define WB_SEL_WIDTH `WB_DATA_WIDTH/8
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`define WB_TAG_WIDTH 4
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`define WB_TAG_WIDTH 5
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`define WB_ADDR_TYPE [(`WB_ADDR_WIDTH - 1):0]
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`define WB_ADDR_TYPE [(`WB_ADDR_WIDTH - 1):0]
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`define WB_DATA_TYPE [(`WB_DATA_WIDTH - 1):0]
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`define WB_DATA_TYPE [(`WB_DATA_WIDTH - 1):0]
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`define WB_SEL_TYPE [(`WB_SEL_WIDTH - 1):0]
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`define WB_SEL_TYPE [(`WB_SEL_WIDTH - 1):0]
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`define WB_TAG_TYPE [(`WB_TAG_WIDTH - 1):0]
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`define WB_TAG_TYPE [(`WB_TAG_WIDTH - 1):0]
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