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`define STOP_ON_FAILURE
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`define STOP_ON_FAILURE
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`ifdef REGRESSION
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`ifdef REGRESSION
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`else // Following DEFINES are used only without regression testing (together with pci_user_constants) !!!
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`else // Following DEFINES are used only without regression testing (together with pci_user_constants) !!!
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// wishbone frequncy in GHz
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// wishbone frequncy in GHz
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`define WB_FREQ 0.025
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`define WB_FREQ 0.05
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// values of image registers of PCI bridge device - valid are only upper 20 bits, others must be ZERO !
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// values of image registers of PCI bridge device - valid are only upper 20 bits, others must be ZERO !
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`define TAR0_BASE_ADDR_0 32'h1000_0000
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`define TAR0_BASE_ADDR_0 32'h1000_0000
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`define TAR0_BASE_ADDR_1 32'h2000_0000
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`define TAR0_BASE_ADDR_1 32'h2000_0000
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`define TAR0_BASE_ADDR_2 32'h3000_0000
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`define TAR0_BASE_ADDR_2 32'h4000_0000
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`define TAR0_BASE_ADDR_3 32'h4000_0000
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`define TAR0_BASE_ADDR_3 32'h6000_0000
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`define TAR0_BASE_ADDR_4 32'h5000_0000
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`define TAR0_BASE_ADDR_4 32'h8000_0000
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`define TAR0_BASE_ADDR_5 32'h6000_0000
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`define TAR0_BASE_ADDR_5 32'hA000_0000
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`define TAR0_ADDR_MASK_0 32'hFFFF_F000 // when BA0 is used to access configuration space, this is NOT important!
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`define TAR0_ADDR_MASK_0 32'hFFFF_F000 // when BA0 is used to access configuration space, this is NOT important!
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`define TAR0_ADDR_MASK_1 32'hFFFF_F000
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`define TAR0_ADDR_MASK_1 32'hFFFF_F000
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`define TAR0_ADDR_MASK_2 32'hFFFF_F000
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`define TAR0_ADDR_MASK_2 32'hFFFF_F000
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`define TAR0_ADDR_MASK_3 32'hFFFF_F000
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`define TAR0_ADDR_MASK_3 32'hFFFF_F000
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`define TAR0_ADDR_MASK_4 32'hFFFF_F000
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`define TAR0_ADDR_MASK_4 32'hFFFF_F000
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`define TAR0_ADDR_MASK_5 32'hFFFF_F000
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`define TAR0_ADDR_MASK_5 32'hFFFF_F000
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`define TAR0_TRAN_ADDR_0 32'h5000_0000 // when BA0 is used to access configuration space, this is NOT important!
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`define TAR0_TRAN_ADDR_0 32'hC000_0000 // when BA0 is used to access configuration space, this is NOT important!
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`define TAR0_TRAN_ADDR_1 32'h4000_0000
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`define TAR0_TRAN_ADDR_1 32'hA000_0000
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`define TAR0_TRAN_ADDR_2 32'h3000_0000
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`define TAR0_TRAN_ADDR_2 32'h8000_0000
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`define TAR0_TRAN_ADDR_3 32'h2000_0000
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`define TAR0_TRAN_ADDR_3 32'h6000_0000
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`define TAR0_TRAN_ADDR_4 32'h1000_0000
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`define TAR0_TRAN_ADDR_4 32'h4000_0000
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`define TAR0_TRAN_ADDR_5 32'h0000_0000
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`define TAR0_TRAN_ADDR_5 32'h2000_0000
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// values of image registers of PCI behavioral target devices !
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// values of image registers of PCI behavioral target devices !
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`define BEH_TAR1_MEM_START 32'h7000_0000
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`define BEH_TAR1_MEM_START 32'hC000_0000
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`define BEH_TAR1_MEM_END 32'h7000_0FFF
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`define BEH_TAR1_MEM_END 32'hC000_0FFF
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`define BEH_TAR1_IO_START 32'h8000_0001
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`define BEH_TAR1_IO_START 32'hD000_0001
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`define BEH_TAR1_IO_END 32'h8000_0FFF
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`define BEH_TAR1_IO_END 32'hD000_0FFF
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`define BEH_TAR2_MEM_START 32'h9000_0000
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`define BEH_TAR2_MEM_START 32'hE000_0000
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`define BEH_TAR2_MEM_END 32'h9000_0FFF
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`define BEH_TAR2_MEM_END 32'hE000_0FFF
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`define BEH_TAR2_IO_START 32'hA000_0001
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`define BEH_TAR2_IO_START 32'hF000_0001
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`define BEH_TAR2_IO_END 32'hA000_0FFF
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`define BEH_TAR2_IO_END 32'hF000_0FFF
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`endif
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`endif
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//===================================================================================
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//===================================================================================
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// User-unchangeable testbench defines (constants)
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// User-unchangeable testbench defines (constants)
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//===================================================================================
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//===================================================================================
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// setup and hold time definitions for WISHBONE - used in BFMs for signal generation
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// setup and hold time definitions for WISHBONE - used in BFMs for signal generation
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`define Tsetup 2
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`define Tsetup 0.5
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`define Thold 2
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`define Thold 0.5
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// how many clock cycles should model wait for design's response - integer 32 bit value
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// how many clock cycles should model wait for design's response - integer 32 bit value
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`define WAIT_FOR_RESPONSE 6
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`define WAIT_FOR_RESPONSE 6
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// maximum number of transactions allowed in single call to block or cab transfer routines
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// maximum number of transactions allowed in single call to block or cab transfer routines
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`define MAX_BLK_SIZE 1024
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`define MAX_BLK_SIZE 512
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// maximum retry terminations allows for WISHBONE master to repeat an access
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// maximum retry terminations allows for WISHBONE master to repeat an access
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`define WB_TB_MAX_RTY 1000
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`define WB_TB_MAX_RTY 10000
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// some common types and defines
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// some common types and defines
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`define WB_ADDR_WIDTH 32
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`define WB_ADDR_WIDTH 32
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`define WB_DATA_WIDTH 32
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`define WB_DATA_WIDTH 32
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