URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_7/] [bench/] [verilog/] [pci_testbench_defines.v] - Diff between revs 26 and 45

Rev 26	Rev 45
Line 41...	Line 41...

`define BEH_TAR2_MEM_START 32'hE000_0000	`define BEH_TAR2_MEM_START 32'hE000_0000
`define BEH_TAR2_MEM_END 32'hE000_0FFF	`define BEH_TAR2_MEM_END 32'hE000_0FFF
`define BEH_TAR2_IO_START 32'hF000_0001	`define BEH_TAR2_IO_START 32'hF000_0001
`define BEH_TAR2_IO_END 32'hF000_0FFF	`define BEH_TAR2_IO_END 32'hF000_0FFF

	`// IDSEL lines of each individual Target is connected to one address line`
	`// following defines set the address line IDSEL is connected to`
	`// TAR0 = DUT - bridge`
	`// TAR1 = behavioral target 1`
	`// TAR2 = behavioral target 2`

	`define TAR0_IDSEL_INDEX 11
	`define TAR1_IDSEL_INDEX 12
	`define TAR2_IDSEL_INDEX 13

	`// next 3 defines are derived from previous three defines`
	`define TAR0_IDSEL_ADDR (32'h0000_0001 << `TAR0_IDSEL_INDEX)
	`define TAR1_IDSEL_ADDR (32'h0000_0001 << `TAR1_IDSEL_INDEX)
	`define TAR2_IDSEL_ADDR (32'h0000_0001 << `TAR2_IDSEL_INDEX)
`endif	`endif

`//===================================================================================`	`//===================================================================================`
`// User-unchangeable testbench defines (constants)`	`// User-unchangeable testbench defines (constants)`
`//===================================================================================`	`//===================================================================================`