URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_7/] [bench/] [verilog/] [pci_testbench_defines.v] - Diff between revs 45 and 54

Rev 45	Rev 54
Line 63...	Line 63...
`//===================================================================================`	`//===================================================================================`
`// User-unchangeable testbench defines (constants)`	`// User-unchangeable testbench defines (constants)`
`//===================================================================================`	`//===================================================================================`

`// setup and hold time definitions for WISHBONE - used in BFMs for signal generation`	`// setup and hold time definitions for WISHBONE - used in BFMs for signal generation`
`define Tsetup 0.5	`define Tsetup 3
`define Thold 0.5	`define Thold 1

`// how many clock cycles should model wait for design's response - integer 32 bit value`	`// how many clock cycles should model wait for design's response - integer 32 bit value`
`define WAIT_FOR_RESPONSE 6	`define WAIT_FOR_RESPONSE 6

`// maximum number of transactions allowed in single call to block or cab transfer routines`	`// maximum number of transactions allowed in single call to block or cab transfer routines`