Line 6... |
Line 6... |
// define whether or not testbench should stop executing after error is detected
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// define whether or not testbench should stop executing after error is detected
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`define STOP_ON_FAILURE
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`define STOP_ON_FAILURE
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`ifdef REGRESSION
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`ifdef REGRESSION
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`else // Following DEFINES are used only without regression testing (together with pci_user_constants) !!!
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`else // Following DEFINES are used only without regression testing (together with pci_user_constants) !!!
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// next two defines are used to generate clocks
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// only one at the time can be defined, otherwise testbench won't work
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// they are used to generate both clocks with same period and phase shift of define's value in nano seconds
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//`define PCI_CLOCK_FOLLOWS_WB_CLOCK 1
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`define WB_CLOCK_FOLLOWS_PCI_CLOCK 2
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// wishbone frequncy in GHz
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// wishbone frequncy in GHz
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`define WB_FREQ 0.05
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`define WB_FREQ 0.033
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// values of image registers of PCI bridge device - valid are only upper 20 bits, others must be ZERO !
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// values of image registers of PCI bridge device - valid are only upper 20 bits, others must be ZERO !
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`define TAR0_BASE_ADDR_0 32'h1000_0000
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`define TAR0_BASE_ADDR_0 32'h1000_0000
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`define TAR0_BASE_ADDR_1 32'h2000_0000
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`define TAR0_BASE_ADDR_1 32'h2000_0000
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`define TAR0_BASE_ADDR_2 32'h4000_0000
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`define TAR0_BASE_ADDR_2 32'h4000_0000
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Line 56... |
Line 64... |
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// next 3 defines are derived from previous three defines
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// next 3 defines are derived from previous three defines
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`define TAR0_IDSEL_ADDR (32'h0000_0001 << `TAR0_IDSEL_INDEX)
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`define TAR0_IDSEL_ADDR (32'h0000_0001 << `TAR0_IDSEL_INDEX)
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`define TAR1_IDSEL_ADDR (32'h0000_0001 << `TAR1_IDSEL_INDEX)
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`define TAR1_IDSEL_ADDR (32'h0000_0001 << `TAR1_IDSEL_INDEX)
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`define TAR2_IDSEL_ADDR (32'h0000_0001 << `TAR2_IDSEL_INDEX)
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`define TAR2_IDSEL_ADDR (32'h0000_0001 << `TAR2_IDSEL_INDEX)
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`define DISABLE_COMPLETION_EXPIRED_TESTS
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`endif
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`endif
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//===================================================================================
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//===================================================================================
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// User-unchangeable testbench defines (constants)
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// User-unchangeable testbench defines (constants)
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//===================================================================================
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//===================================================================================
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Line 157... |
Line 167... |
`define WB_TRANSFER_AUTO_RTY [8]
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`define WB_TRANSFER_AUTO_RTY [8]
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`define WB_TRANSFER_CAB [9]
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`define WB_TRANSFER_CAB [9]
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`define INIT_WAITS [3:0]
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`define INIT_WAITS [3:0]
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`define SUBSEQ_WAITS [7:4]
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`define SUBSEQ_WAITS [7:4]
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No newline at end of file
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No newline at end of file
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