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[/] [pci/] [tags/] [rel_7/] [bench/] [verilog/] [pci_testbench_defines.v] - Diff between revs 54 and 63

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Rev 54 Rev 63
Line 6... Line 6...
// define whether or not testbench should stop executing after error is detected
// define whether or not testbench should stop executing after error is detected
`define STOP_ON_FAILURE
`define STOP_ON_FAILURE
 
 
`ifdef REGRESSION
`ifdef REGRESSION
`else // Following DEFINES are used only without regression testing (together with pci_user_constants) !!!
`else // Following DEFINES are used only without regression testing (together with pci_user_constants) !!!
 
 
 
    // next two defines are used to generate clocks
 
    // only one at the time can be defined, otherwise testbench won't work
 
    // they are used to generate both clocks with same period and phase shift of define's value in nano seconds
 
 
 
    //`define PCI_CLOCK_FOLLOWS_WB_CLOCK 1
 
    `define WB_CLOCK_FOLLOWS_PCI_CLOCK 2
 
 
    // wishbone frequncy in GHz
    // wishbone frequncy in GHz
    `define WB_FREQ 0.05
    `define WB_FREQ 0.033
 
 
    // values of image registers of PCI bridge device - valid are only upper 20 bits, others must be ZERO !
    // values of image registers of PCI bridge device - valid are only upper 20 bits, others must be ZERO !
    `define TAR0_BASE_ADDR_0    32'h1000_0000
    `define TAR0_BASE_ADDR_0    32'h1000_0000
    `define TAR0_BASE_ADDR_1    32'h2000_0000
    `define TAR0_BASE_ADDR_1    32'h2000_0000
    `define TAR0_BASE_ADDR_2    32'h4000_0000
    `define TAR0_BASE_ADDR_2    32'h4000_0000
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    // next 3 defines are derived from previous three defines
    // next 3 defines are derived from previous three defines
    `define TAR0_IDSEL_ADDR     (32'h0000_0001 << `TAR0_IDSEL_INDEX)
    `define TAR0_IDSEL_ADDR     (32'h0000_0001 << `TAR0_IDSEL_INDEX)
    `define TAR1_IDSEL_ADDR     (32'h0000_0001 << `TAR1_IDSEL_INDEX)
    `define TAR1_IDSEL_ADDR     (32'h0000_0001 << `TAR1_IDSEL_INDEX)
    `define TAR2_IDSEL_ADDR     (32'h0000_0001 << `TAR2_IDSEL_INDEX)
    `define TAR2_IDSEL_ADDR     (32'h0000_0001 << `TAR2_IDSEL_INDEX)
 
 
 
    `define DISABLE_COMPLETION_EXPIRED_TESTS
`endif
`endif
 
 
//===================================================================================
//===================================================================================
//  User-unchangeable testbench defines (constants)
//  User-unchangeable testbench defines (constants)
//===================================================================================
//===================================================================================
Line 157... Line 167...
`define WB_TRANSFER_AUTO_RTY [8]
`define WB_TRANSFER_AUTO_RTY [8]
`define WB_TRANSFER_CAB      [9]
`define WB_TRANSFER_CAB      [9]
`define INIT_WAITS           [3:0]
`define INIT_WAITS           [3:0]
`define SUBSEQ_WAITS         [7:4]
`define SUBSEQ_WAITS         [7:4]
 
 
 
 
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