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[/] [pci/] [tags/] [rel_7/] [bench/] [verilog/] [pci_testbench_defines.v] - Diff between revs 63 and 66
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Rev 63 |
Rev 66 |
Line 65... |
Line 65... |
// next 3 defines are derived from previous three defines
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// next 3 defines are derived from previous three defines
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`define TAR0_IDSEL_ADDR (32'h0000_0001 << `TAR0_IDSEL_INDEX)
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`define TAR0_IDSEL_ADDR (32'h0000_0001 << `TAR0_IDSEL_INDEX)
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`define TAR1_IDSEL_ADDR (32'h0000_0001 << `TAR1_IDSEL_INDEX)
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`define TAR1_IDSEL_ADDR (32'h0000_0001 << `TAR1_IDSEL_INDEX)
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`define TAR2_IDSEL_ADDR (32'h0000_0001 << `TAR2_IDSEL_INDEX)
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`define TAR2_IDSEL_ADDR (32'h0000_0001 << `TAR2_IDSEL_INDEX)
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`define DISABLE_COMPLETION_EXPIRED_TESTS
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//`define DISABLE_COMPLETION_EXPIRED_TESTS
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`endif
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`endif
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//===================================================================================
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//===================================================================================
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// User-unchangeable testbench defines (constants)
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// User-unchangeable testbench defines (constants)
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//===================================================================================
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//===================================================================================
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