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[/] [pci/] [tags/] [rel_7/] [bench/] [verilog/] [pci_testbench_defines.v] - Diff between revs 63 and 66

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Rev 63 Rev 66
Line 65... Line 65...
    // next 3 defines are derived from previous three defines
    // next 3 defines are derived from previous three defines
    `define TAR0_IDSEL_ADDR     (32'h0000_0001 << `TAR0_IDSEL_INDEX)
    `define TAR0_IDSEL_ADDR     (32'h0000_0001 << `TAR0_IDSEL_INDEX)
    `define TAR1_IDSEL_ADDR     (32'h0000_0001 << `TAR1_IDSEL_INDEX)
    `define TAR1_IDSEL_ADDR     (32'h0000_0001 << `TAR1_IDSEL_INDEX)
    `define TAR2_IDSEL_ADDR     (32'h0000_0001 << `TAR2_IDSEL_INDEX)
    `define TAR2_IDSEL_ADDR     (32'h0000_0001 << `TAR2_IDSEL_INDEX)
 
 
    `define DISABLE_COMPLETION_EXPIRED_TESTS
    //`define DISABLE_COMPLETION_EXPIRED_TESTS
`endif
`endif
 
 
//===================================================================================
//===================================================================================
//  User-unchangeable testbench defines (constants)
//  User-unchangeable testbench defines (constants)
//===================================================================================
//===================================================================================

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