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[/] [pci/] [tags/] [rel_7/] [bench/] [verilog/] [pci_testbench_defines.v] - Diff between revs 73 and 92

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Rev 73 Rev 92
Line 65... Line 65...
    // next 3 defines are derived from previous three defines
    // next 3 defines are derived from previous three defines
    `define TAR0_IDSEL_ADDR     (32'h0000_0001 << `TAR0_IDSEL_INDEX)
    `define TAR0_IDSEL_ADDR     (32'h0000_0001 << `TAR0_IDSEL_INDEX)
    `define TAR1_IDSEL_ADDR     (32'h0000_0001 << `TAR1_IDSEL_INDEX)
    `define TAR1_IDSEL_ADDR     (32'h0000_0001 << `TAR1_IDSEL_INDEX)
    `define TAR2_IDSEL_ADDR     (32'h0000_0001 << `TAR2_IDSEL_INDEX)
    `define TAR2_IDSEL_ADDR     (32'h0000_0001 << `TAR2_IDSEL_INDEX)
 
 
    `define DISABLE_COMPLETION_EXPIRED_TESTS
    //`define DISABLE_COMPLETION_EXPIRED_TESTS
`endif
`endif
 
 
//===================================================================================
//===================================================================================
//  User-unchangeable testbench defines (constants)
//  User-unchangeable testbench defines (constants)
//===================================================================================
//===================================================================================
Line 80... Line 80...
 
 
// how many clock cycles should model wait for design's response - integer 32 bit value
// how many clock cycles should model wait for design's response - integer 32 bit value
`define WAIT_FOR_RESPONSE 6
`define WAIT_FOR_RESPONSE 6
 
 
// maximum number of transactions allowed in single call to block or cab transfer routines
// maximum number of transactions allowed in single call to block or cab transfer routines
`define MAX_BLK_SIZE  1024
`define MAX_BLK_SIZE  4096
 
 
// maximum retry terminations allows for WISHBONE master to repeat an access
// maximum retry terminations allows for WISHBONE master to repeat an access
`define WB_TB_MAX_RTY 10000
`define WB_TB_MAX_RTY 10000
 
 
 
 
Line 154... Line 154...
`define CYC_ERR [3]
`define CYC_ERR [3]
`define CYC_RESPONSE [3:1]
`define CYC_RESPONSE [3:1]
`define CYC_ACTUAL_TRANSFER [35:4]
`define CYC_ACTUAL_TRANSFER [35:4]
 
 
// block transfer flags
// block transfer flags
`define WB_TRANSFER_FLAGS [41:0]
`define WB_TRANSFER_FLAGS [42:0]
// consists of:
// consists of:
// - number of transfer cycles to perform
// - number of transfer cycles to perform
// - flag that enables retry termination handling - if disabled, block transfer routines will return on any termination other than acknowledge
// - flag that enables retry termination handling - if disabled, block transfer routines will return on any termination other than acknowledge
// - flag indicating CAB transfer is to be performed - ignored by all single transfer routines
// - flag indicating CAB transfer is to be performed - ignored by all single transfer routines
// - number of initial wait states to insert
// - number of initial wait states to insert
// - number of subsequent wait states to insert
// - number of subsequent wait states to insert
 
`define WB_FAST_B2B          [42]
`define WB_TRANSFER_SIZE     [41:10]
`define WB_TRANSFER_SIZE     [41:10]
`define WB_TRANSFER_AUTO_RTY [8]
`define WB_TRANSFER_AUTO_RTY [8]
`define WB_TRANSFER_CAB      [9]
`define WB_TRANSFER_CAB      [9]
`define INIT_WAITS           [3:0]
`define INIT_WAITS           [3:0]
`define SUBSEQ_WAITS         [7:4]
`define SUBSEQ_WAITS         [7:4]

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