| Line 13... |
Line 13... |
TRDY,
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TRDY,
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STOP,
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STOP,
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PAR
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PAR
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);
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);
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parameter normal = 0 ;
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parameter disconnect = 1 ;
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parameter retry = 2 ;
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parameter target_abort = 3 ;
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parameter master_abort = 4 ;
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parameter error = 5 ;
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input CLK ;
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input CLK ;
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output [31:0] AD ;
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inout [31:0] AD ;
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output [3:0] CBE ;
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inout [3:0] CBE ;
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input RST ;
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input RST ;
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output REQ ;
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output REQ ;
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input GNT ;
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input GNT ;
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output FRAME ;
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inout FRAME ;
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output IRDY ;
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inout IRDY ;
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input DEVSEL ;
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input DEVSEL ;
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input TRDY ;
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input TRDY ;
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input STOP ;
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input STOP ;
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output PAR ;
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inout PAR ;
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reg [31:0] AD_int ;
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reg AD_en ;
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reg [3:0] CBE_int ;
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reg CBE_en ;
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reg FRAME_int ;
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reg FRAME_en ;
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reg IRDY_int ;
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reg IRDY_en ;
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reg PAR_int ;
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reg PAR_en ;
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assign AD = AD_en ? AD_int : 32'hzzzz_zzzz ;
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assign CBE = CBE_en ? CBE_int : 4'hz ;
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assign FRAME = FRAME_en ? FRAME_int : 1'bz ;
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assign IRDY = IRDY_en ? IRDY_int : 1'bz ;
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assign PAR = PAR_en ? PAR_int : 1'bz ;
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reg [31:0] AD ;
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reg [3:0] CBE ;
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reg REQ ;
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reg REQ ;
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reg FRAME ;
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reg IRDY ;
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event e_finish_transaction ;
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reg PAR ;
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event e_transfers_done ;
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reg write ;
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reg make_parity_error_after_last_dataphase ;
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initial
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initial
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begin
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begin
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REQ = 1'b1 ;
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REQ = 1'b1 ;
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AD = 32'hzzzz_zzzz ;
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AD_en = 1'b0 ;
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CBE = 4'bzzzz ;
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CBE_en = 1'b0 ;
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FRAME = 1'bz ;
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FRAME_en = 1'b0 ;
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IRDY = 1'bz ;
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IRDY_en = 1'b0 ;
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PAR = 1'bz ;
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PAR_en = 1'b0 ;
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write = 1'b0 ;
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make_parity_error_after_last_dataphase = 1'b0 ;
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end
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end
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task master_reference ;
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task unsupported_reference ;
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input [31:0] addr1 ;
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input [31:0] addr1 ;
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input [31:0] addr2 ;
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input [31:0] addr2 ;
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input [3:0] bc1 ;
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input [3:0] bc1 ;
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input [3:0] bc2 ;
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input [3:0] bc2 ;
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input [3:0] be ;
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input [3:0] be ;
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| Line 55... |
Line 86... |
input make_addr_perr1 ;
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input make_addr_perr1 ;
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input make_addr_perr2 ;
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input make_addr_perr2 ;
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output ok ;
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output ok ;
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integer i ;
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integer i ;
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reg dual_address ;
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reg dual_address ;
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begin
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reg [2:0] received_termination ;
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begin:main
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ok = 1 ;
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ok = 1 ;
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dual_address = (bc1 == `BC_DUAL_ADDR_CYC) ;
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dual_address = (bc1 == `BC_DUAL_ADDR_CYC) ;
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@(posedge CLK) ;
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while( GNT == 1 )
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get_bus_ownership(ok) ;
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if (ok !== 1'b1)
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disable main ;
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addr_phase1(addr1, bc1) ;
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if ( dual_address )
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begin
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begin
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REQ <= #1 1'b0 ;
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write = bc2[0] ;
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@(posedge CLK) ;
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addr_phase2(addr2, bc2, make_addr_perr1) ;
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first_and_last_data_phase(bc2[0], data, be, make_addr_perr2, 1'b0, received_termination) ;
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finish_transaction(bc2[0], 1'b0) ;
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end
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else
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begin
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write = bc1[0] ;
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first_and_last_data_phase(bc1[0], data, be, make_addr_perr1, 1'b0, received_termination) ;
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finish_transaction(bc1[0], 1'b0) ;
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end
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end
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REQ <= #1 1'b1 ;
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if (received_termination !== master_abort)
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FRAME <= #1 1'b0 ;
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begin
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AD <= #1 addr1 ;
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ok = 0 ;
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CBE <= #1 bc1 ;
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end
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end
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endtask // master_reference
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// end of first address cycle
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// task added for target overflow testing
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@(posedge CLK) ;
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// master writes the addresses to the coresponding locations
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PAR <= #1 ^{AD, CBE, make_addr_perr1} ;
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task normal_write_transfer ;
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if ( dual_address )
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input [31:0] start_address ;
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input [3:0] bus_command ;
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input [31:0] size ;
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input [2:0] wait_cycles ;
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output [31:0] actual_transfer ;
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output [2:0] received_termination ;
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reg ok ;
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reg [31:0] current_address ;
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begin:main
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write = 1'b1 ;
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get_bus_ownership (ok) ;
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if (ok !== 1'b1)
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begin
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begin
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IRDY <= #1 1'b1 ;
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received_termination = error ;
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AD <= #1 addr2 ;
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disable main ;
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CBE <= #1 bc2 ;
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end
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make_parity_error_after_last_dataphase = 1'b0 ;
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addr_phase1(start_address, bus_command) ;
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actual_transfer = 0 ;
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if (size == 1)
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begin
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first_and_last_data_phase (1'b1, ~start_address, 4'hF, 1'b0, 1'b0, received_termination) ;
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if ((received_termination == normal) || (received_termination == disconnect))
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actual_transfer = 1 ;
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-> e_finish_transaction ;
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end
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end
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else
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else
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begin
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begin
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IRDY <= #1 1'b0 ;
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current_address = start_address ;
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FRAME <= #1 1'b1 ;
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first_data_phase (1'b1, ~start_address, 4'hF, 1'b0, 1'b0, received_termination) ;
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CBE <= #1 be ;
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if ((received_termination == normal) || (received_termination == disconnect))
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if ( bc1[0] )
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actual_transfer = 1 ;
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AD <= #1 data ;
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if (received_termination == master_abort)
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begin
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-> e_transfers_done ;
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end
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while ((actual_transfer < (size - 1)) && (received_termination == normal))
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begin
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current_address = current_address + 4 ;
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insert_waits(1'b1, wait_cycles, received_termination) ;
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if (received_termination === normal)
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begin
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subsequent_data_phase(1'b1, ~current_address, 4'hF, 1'b0, received_termination) ;
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if ((received_termination == normal) || (received_termination == disconnect))
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actual_transfer = actual_transfer + 1 ;
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end
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end
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if (received_termination == normal)
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begin
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insert_waits(1'b1, wait_cycles, received_termination) ;
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if (received_termination === normal)
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begin
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last_data_phase(1'b1, ~current_address, 4'hF, 1'b0, received_termination) ;
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if ((received_termination == normal) || (received_termination == disconnect))
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actual_transfer = actual_transfer + 1 ;
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-> e_finish_transaction ;
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end
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else
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-> e_transfers_done ;
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end
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else
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else
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AD <= #1 32'hzzzz_zzzz ;
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-> e_transfers_done ;
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end
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end
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end
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endtask // normal_write_transfer
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task get_bus_ownership ;
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output ok ;
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integer deadlock ;
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begin
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deadlock = 0 ;
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@(posedge CLK) ;
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@(posedge CLK) ;
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CBE <= #1 be ;
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while( ((GNT !== 0) || (FRAME !== 1'b1) || (IRDY !== 1'b1)) && (deadlock < 5000) )
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if ( dual_address )
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begin
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REQ <= #6 1'b0 ;
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@(posedge CLK) ;
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deadlock = deadlock + 1 ;
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end
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if (GNT !== 0)
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begin
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begin
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PAR <= #1 ^{AD, CBE, make_addr_perr2} ;
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$display("*E, PCI Master could not get ownership of the bus in 5000 cycles") ;
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IRDY <= #1 1'b0 ;
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ok = 0 ;
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FRAME <= #1 1'b1 ;
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end
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if ( bc2[0] )
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AD <= #1 data ;
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else
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else
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AD <= #1 32'hzzzz_zzzz ;
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begin
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ok = 1 ;
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end
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REQ <= #6 1'b1 ;
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end
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end
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endtask // get_bus_ownership
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task addr_phase1 ;
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input [31:0] address ;
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input [3:0] bus_command ;
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begin
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FRAME_en <= #6 1'b1 ;
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FRAME_int <= #6 1'b0 ;
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AD_en <= #6 1'b1 ;
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AD_int <= #6 address ;
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CBE_en <= #6 1'b1 ;
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CBE_int <= #6 bus_command ;
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@(posedge CLK) ;
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end
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endtask // addr_phase1
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task addr_phase2 ;
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input [31:0] address ;
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input [3:0] bus_command ;
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input make_parity_error;
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begin
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PAR_int <= #6 ^{AD, CBE, make_parity_error} ;
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PAR_en <= #6 1'b1 ;
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AD_int <= #6 address ;
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CBE_int <= #6 bus_command ;
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@(posedge CLK) ;
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end
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endtask
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task first_and_last_data_phase ;
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input rw ;
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input [31:0] data ;
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input [3:0] be ;
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input make_addr_parity_error ;
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input make_data_parity_error ;
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output [2:0] received_termination ;
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integer i ;
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begin
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FRAME_int <= #6 1'b1 ;
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first_data_phase (rw, data, be, make_addr_parity_error, make_data_parity_error, received_termination) ;
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end
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endtask // first_and_last_data_phase
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task first_data_phase ;
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input rw ;
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input [31:0] data ;
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input [3:0] be ;
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input make_addr_parity_error ;
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input make_data_parity_error ;
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output [2:0] received_termination ;
|
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integer i ;
|
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begin
|
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PAR_int <= #6 ^{AD, CBE, make_addr_parity_error} ;
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PAR_en <= #6 1'b1 ;
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IRDY_en <= #6 1'b1 ;
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IRDY_int <= #6 1'b0 ;
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CBE_int <= #6 be ;
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if (rw)
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AD_int <= #6 data ;
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else
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else
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AD_en <= #6 1'b0 ;
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@(posedge CLK) ;
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if (!rw)
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PAR_en <= #6 1'b0 ;
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else
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PAR_int <= #6 ^{AD, CBE, make_data_parity_error} ;
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|
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i = 1 ;
|
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while ( (i < 5) && (DEVSEL === 1'b1) )
|
|
begin
|
|
@(posedge CLK) ;
|
|
i = i + 1 ;
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|
end
|
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|
|
if (DEVSEL === 1'b1)
|
begin
|
begin
|
if ( bc1[0] )
|
received_termination = master_abort ;
|
PAR <= #1 ^{AD, CBE} ;
|
end
|
else
|
else
|
PAR <= #1 1'bz ;
|
begin
|
|
get_termination(received_termination);
|
|
end
|
|
end
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endtask // first_data_phase
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|
|
task subsequent_data_phase ;
|
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input rw ;
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input [31:0] data ;
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input [3:0] be ;
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input make_parity_error ;
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output [2:0] received_termination ;
|
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begin
|
|
if (rw)
|
|
begin
|
|
PAR_int <= #6 ^{AD, CBE, make_parity_error} ;
|
|
AD_int <= #6 data ;
|
end
|
end
|
|
|
|
IRDY_int <= #6 1'b0 ;
|
|
CBE_int <= #6 be ;
|
@(posedge CLK) ;
|
@(posedge CLK) ;
|
if ( AD[31] !== 1'bz )
|
get_termination(received_termination);
|
PAR <= #1 ^{AD, CBE} ;
|
end
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endtask // subsequent_data_phase
|
|
|
|
task last_data_phase ;
|
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input rw ;
|
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input [31:0] data ;
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input [3:0] be ;
|
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input make_parity_error ;
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output [2:0] received_termination ;
|
|
begin
|
|
FRAME_int <= #6 1'b1 ;
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|
IRDY_int <= #6 1'b0 ;
|
|
if (rw)
|
|
begin
|
|
PAR_int <= #6 ^{AD, CBE, make_parity_error} ;
|
|
AD_int <= #6 data ;
|
|
end
|
|
|
|
CBE_int <= #6 be ;
|
|
|
|
@(posedge CLK);
|
|
get_termination(received_termination);
|
|
end
|
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endtask // subsequent_data_phase
|
|
|
|
task get_termination ;
|
|
output [2:0] received_termination ;
|
|
begin
|
|
while ((TRDY === 1'b1) && (STOP === 1'b1))
|
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@(posedge CLK) ;
|
|
|
|
if ( DEVSEL !== 1'b0 )
|
|
received_termination = target_abort ;
|
|
else if (TRDY !== 1'b1)
|
|
begin
|
|
if (STOP !== 1'b1)
|
|
received_termination = disconnect ;
|
else
|
else
|
PAR <= #1 1'bz ;
|
received_termination = normal ;
|
|
end
|
|
else
|
|
received_termination = retry ;
|
|
end
|
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endtask // get_termination
|
|
|
i = 0 ; // Checking for Master Abort
|
task finish_transaction ;
|
while ( (DEVSEL === 1) && (STOP === 1) && (i < 6) )
|
input rw ;
|
|
input make_parity_error ;
|
begin
|
begin
|
|
if (rw)
|
|
PAR_int <= #6 ^{AD, CBE, make_parity_error} ;
|
|
|
|
IRDY_int <= #6 1'b1 ;
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FRAME_en <= #6 1'b0 ;
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AD_en <= #6 1'b0 ;
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CBE_en <= #6 1'b0 ;
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@(posedge CLK) ;
|
@(posedge CLK) ;
|
i = i + 1 ;
|
PAR_en <= #6 1'b0 ;
|
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IRDY_en <= #6 1'b0 ;
|
|
end
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endtask // finish_transaction
|
|
|
|
always@(e_finish_transaction)
|
|
begin
|
|
finish_transaction (write, make_parity_error_after_last_dataphase) ;
|
end
|
end
|
|
|
if ( (DEVSEL !== 1) || (STOP !== 1) )
|
always@(e_transfers_done)
|
begin
|
begin
|
ok = 0 ; // If NO Master abort, then NOT OK!
|
|
|
if (FRAME !== 1'b1)
|
|
begin
|
|
FRAME_int <= #6 1'b1 ;
|
|
IRDY_int <= #6 1'b0 ;
|
|
if (write)
|
|
PAR_int <= #6 ^{CBE, AD} ;
|
|
|
|
@(posedge CLK) ;
|
end
|
end
|
|
|
FRAME <= #1 1'bz ;
|
-> e_finish_transaction ;
|
IRDY <= #1 1'b1 ;
|
end
|
AD <= #1 32'hzzzz_zzzz ;
|
|
CBE <= #1 4'hz ;
|
task insert_waits ;
|
|
input rw ;
|
|
input [2:0] wait_cycles ;
|
|
output [2:0] termination ;
|
|
reg [2:0] wait_cycles_left ;
|
|
reg stop_without_trdy_received ;
|
|
begin
|
|
stop_without_trdy_received = 1'b0 ;
|
|
wait_cycles_left = wait_cycles ;
|
|
|
|
termination = normal ;
|
|
|
|
PAR_int <= #6 ^{AD, CBE} ;
|
|
|
|
for (wait_cycles_left = wait_cycles ; (wait_cycles_left > 0) && !stop_without_trdy_received ; wait_cycles_left = wait_cycles_left - 1'b1)
|
|
begin
|
|
IRDY_int <= #6 1'b1 ;
|
@(posedge CLK) ;
|
@(posedge CLK) ;
|
IRDY <= #1 1'bz ;
|
|
PAR <= #1 1'bz ;
|
PAR_int <= #6 ^{AD, CBE, 1'b1} ;
|
|
|
|
if ((STOP !== 1'b1) && (TRDY !== 1'b0))
|
|
begin
|
|
stop_without_trdy_received = 1'b1 ;
|
|
if (DEVSEL !== 1'b0)
|
|
termination = target_abort ;
|
|
else
|
|
termination = retry ;
|
end
|
end
|
endtask // master_reference
|
end
|
|
end
|
|
endtask // insert_waits
|
endmodule
|
endmodule
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No newline at end of file
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No newline at end of file
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