| Line 37... |
Line 37... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.17 2003/07/29 08:19:47 mihad
|
|
// Found and simulated the problem in the synchronization logic.
|
|
// Repaired the synchronization logic in the FIFOs.
|
|
//
|
// Revision 1.16 2003/06/12 02:30:39 mihad
|
// Revision 1.16 2003/06/12 02:30:39 mihad
|
// Update!
|
// Update!
|
//
|
//
|
// Revision 1.15 2003/03/14 15:33:55 mihad
|
// Revision 1.15 2003/03/14 15:33:55 mihad
|
// Updated acording to RTL changes.
|
// Updated acording to RTL changes.
|
| Line 154... |
Line 158... |
wire [3:0] SEL_I ;
|
wire [3:0] SEL_I ;
|
wire CYC_I ;
|
wire CYC_I ;
|
wire STB_I ;
|
wire STB_I ;
|
wire WE_I ;
|
wire WE_I ;
|
wire CAB_I ;
|
wire CAB_I ;
|
|
wire [2:0] CTI_I ;
|
|
wire [1:0] BTE_I ;
|
wire ACK_O ;
|
wire ACK_O ;
|
wire RTY_O ;
|
wire RTY_O ;
|
wire ERR_O ;
|
wire ERR_O ;
|
|
|
wire [31:0] ADR_O ;
|
wire [31:0] ADR_O ;
|
| Line 195... |
Line 201... |
assign reset_wb = reset ;
|
assign reset_wb = reset ;
|
`endif
|
`endif
|
|
|
`define PCI_BRIDGE_INSTANCE bridge32_top
|
`define PCI_BRIDGE_INSTANCE bridge32_top
|
|
|
|
reg tc_gnt_allow ;
|
|
initial tc_gnt_allow = 1'b0 ;
|
|
|
TOP `PCI_BRIDGE_INSTANCE
|
TOP `PCI_BRIDGE_INSTANCE
|
(
|
(
|
.CLK ( pci_clock),
|
.CLK ( pci_clock),
|
.AD ( AD ),
|
.AD ( AD ),
|
.CBE ( CBE ),
|
.CBE ( CBE ),
|
.RST ( RST ),
|
.RST ( RST ),
|
.INTA ( INTA ),
|
.INTA ( INTA ),
|
.REQ ( MAS0_REQ ),
|
.REQ ( MAS0_REQ ),
|
.GNT ( MAS0_GNT ),
|
.GNT ( MAS0_GNT | tc_gnt_allow),
|
.FRAME ( FRAME ),
|
.FRAME ( FRAME ),
|
.IRDY ( IRDY ),
|
.IRDY ( IRDY ),
|
.IDSEL ( TAR0_IDSEL),
|
.IDSEL ( TAR0_IDSEL),
|
.DEVSEL ( DEVSEL ),
|
.DEVSEL ( DEVSEL ),
|
.TRDY ( TRDY ),
|
.TRDY ( TRDY ),
|
| Line 229... |
Line 238... |
.SEL_I ( SEL_I ),
|
.SEL_I ( SEL_I ),
|
.CYC_I ( CYC_I ),
|
.CYC_I ( CYC_I ),
|
.STB_I ( STB_I ),
|
.STB_I ( STB_I ),
|
.WE_I ( WE_I ),
|
.WE_I ( WE_I ),
|
.CAB_I ( CAB_I),
|
.CAB_I ( CAB_I),
|
|
.CTI_I ( CTI_I),
|
|
.BTE_I ( BTE_I),
|
.ACK_O ( ACK_O ),
|
.ACK_O ( ACK_O ),
|
.RTY_O ( RTY_O ),
|
.RTY_O ( RTY_O ),
|
.ERR_O ( ERR_O ),
|
.ERR_O ( ERR_O ),
|
|
|
// WISHBONE master interface
|
// WISHBONE master interface
|
| Line 261... |
Line 272... |
|
|
WB_MASTER_BEHAVIORAL wishbone_master
|
WB_MASTER_BEHAVIORAL wishbone_master
|
(
|
(
|
.CLK_I(wb_clock),
|
.CLK_I(wb_clock),
|
.RST_I(reset_wb),
|
.RST_I(reset_wb),
|
.TAG_I(4'b0000),
|
.TAG_I(`WB_TAG_WIDTH'd0),
|
.TAG_O(),
|
.TAG_O({CTI_I, BTE_I}),
|
.ACK_I(ACK_O),
|
.ACK_I(ACK_O),
|
.ADR_O(ADR_I),
|
.ADR_O(ADR_I),
|
.CYC_O(CYC_I),
|
.CYC_O(CYC_I),
|
.DAT_I(SDAT_O),
|
.DAT_I(SDAT_O),
|
.DAT_O(SDAT_I),
|
.DAT_O(SDAT_I),
|
| Line 309... |
Line 320... |
.RTY_I(RTY_O),
|
.RTY_I(RTY_O),
|
.SEL_O(SEL_I),
|
.SEL_O(SEL_I),
|
.STB_O(STB_I),
|
.STB_O(STB_I),
|
.WE_O (WE_I),
|
.WE_O (WE_I),
|
.TAG_I({`WB_TAG_WIDTH{1'b0}}),
|
.TAG_I({`WB_TAG_WIDTH{1'b0}}),
|
.TAG_O(),
|
.TAG_O({CTI_I, BTE_I}),
|
.CAB_O(CAB_I),
|
.CAB_O(CAB_I),
|
.log_file_desc ( wbu_mon_log_file_desc )
|
.log_file_desc ( wbu_mon_log_file_desc )
|
) ;
|
) ;
|
|
|
WB_BUS_MON pciu_wb_mon(
|
WB_BUS_MON pciu_wb_mon(
|
| Line 328... |
Line 339... |
.RTY_I(RTY_I),
|
.RTY_I(RTY_I),
|
.SEL_O(SEL_O),
|
.SEL_O(SEL_O),
|
.STB_O(STB_O),
|
.STB_O(STB_O),
|
.WE_O (WE_O),
|
.WE_O (WE_O),
|
.TAG_I({`WB_TAG_WIDTH{1'b0}}),
|
.TAG_I({`WB_TAG_WIDTH{1'b0}}),
|
.TAG_O(),
|
.TAG_O({`WB_TAG_WIDTH{1'b0}}),
|
.CAB_O(CAB_O),
|
.CAB_O(CAB_O),
|
.log_file_desc( pciu_mon_log_file_desc )
|
.log_file_desc( pciu_mon_log_file_desc )
|
) ;
|
) ;
|
|
|
// some aditional signals are needed here because of the arbiter
|
// some aditional signals are needed here because of the arbiter
|
| Line 427... |
Line 438... |
.pci_ext_trdy_l (TRDY),
|
.pci_ext_trdy_l (TRDY),
|
.pci_ext_stop_l (STOP),
|
.pci_ext_stop_l (STOP),
|
.pci_ext_perr_l (PERR),
|
.pci_ext_perr_l (PERR),
|
.pci_ext_serr_l (SERR),
|
.pci_ext_serr_l (SERR),
|
.pci_real_req_l (MAS0_REQ),
|
.pci_real_req_l (MAS0_REQ),
|
.pci_real_gnt_l (MAS0_GNT),
|
.pci_real_gnt_l (MAS0_GNT | tc_gnt_allow),
|
.pci_ext_req_l ({1'b1, MAS3_REQ, MAS2_REQ, MAS1_REQ}),
|
.pci_ext_req_l ({1'b1, MAS3_REQ, MAS2_REQ, MAS1_REQ}),
|
.pci_ext_gnt_l (~arb_grant_out[4:1]),
|
.pci_ext_gnt_l (~arb_grant_out[4:1]),
|
.test_error_event (error_event_int),
|
.test_error_event (error_event_int),
|
.test_observe_r_oe_sigs (r_oe_sigs),
|
.test_observe_r_oe_sigs (r_oe_sigs),
|
.test_observe_0_oe_sigs (6'h00),
|
.test_observe_0_oe_sigs (6'h00),
|
| Line 846... |
Line 857... |
$fdisplay(pci_mon_log_file_desc, "*********************************** Start PCI Bus Monitor log file ******************************************") ;
|
$fdisplay(pci_mon_log_file_desc, "*********************************** Start PCI Bus Monitor log file ******************************************") ;
|
|
|
run_tests ;
|
run_tests ;
|
end
|
end
|
|
|
task fill_memory ;
|
task fill_memory ; //wb_b3_ok
|
integer temp_index ;
|
integer temp_index ;
|
begin
|
begin
|
// fill write memories with random data
|
// fill write memories with random data
|
for( temp_index = 0; temp_index <=1023; temp_index = temp_index + 1 )
|
for( temp_index = 0; temp_index <=1023; temp_index = temp_index + 1 )
|
begin
|
begin
|
| Line 872... |
Line 883... |
reg [2:0] pci_init_waits ;
|
reg [2:0] pci_init_waits ;
|
reg [2:0] wb_subseq_waits ;
|
reg [2:0] wb_subseq_waits ;
|
reg [2:0] pci_subseq_waits ;
|
reg [2:0] pci_subseq_waits ;
|
reg [2:0] tb_target_decode_speed ;
|
reg [2:0] tb_target_decode_speed ;
|
|
|
task run_tests ;
|
task run_tests ; //wb_b3_ok
|
begin
|
begin
|
wb_init_waits = 0;
|
wb_init_waits = 0;
|
pci_init_waits = 0;
|
pci_init_waits = 0;
|
wb_subseq_waits = 0 ;
|
wb_subseq_waits = 0 ;
|
pci_subseq_waits = 0 ;
|
pci_subseq_waits = 0 ;
|
| Line 885... |
Line 896... |
// first - reset logic
|
// first - reset logic
|
do_reset ;
|
do_reset ;
|
|
|
// if BIST is implemented, give it a go
|
// if BIST is implemented, give it a go
|
`ifdef PCI_BIST
|
`ifdef PCI_BIST
|
// run_bist_test ;
|
run_bist_test ;
|
scanb_rst <= #1 1'b1 ;
|
scanb_rst <= #1 1'b1 ;
|
`endif
|
`endif
|
test_initial_conf_values ;
|
test_initial_conf_values ;
|
|
|
next_test_name[79:0] <= "Initing...";
|
next_test_name[79:0] <= "Initing...";
|
| Line 1082... |
Line 1093... |
configure_target(1) ;
|
configure_target(1) ;
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
configure_target(2) ;
|
configure_target(2) ;
|
|
|
`ifdef GUEST
|
`ifdef GUEST
|
configure_bridge_target ;
|
configure_bridge_target ; // b3ok
|
`endif
|
`endif
|
|
|
target_special_corner_case_test ;
|
target_special_corner_case_test ;
|
`endif
|
`endif
|
|
|
| Line 1100... |
Line 1111... |
$fclose(wbu_mon_log_file_desc | pciu_mon_log_file_desc | pci_mon_log_file_desc) ;
|
$fclose(wbu_mon_log_file_desc | pciu_mon_log_file_desc | pci_mon_log_file_desc) ;
|
$stop ;
|
$stop ;
|
end
|
end
|
endtask // run_tests
|
endtask // run_tests
|
|
|
task do_reset;
|
task do_reset; //wb_b3_ok
|
begin
|
begin
|
next_test_name[79:0] <= "Reset.....";
|
next_test_name[79:0] <= "Reset.....";
|
|
|
reset = 1'b1 ;
|
reset = 1'b1 ;
|
#100 ;
|
#100 ;
|
| Line 1132... |
Line 1143... |
/*############################################################################
|
/*############################################################################
|
WB SLAVE UNIT tasks
|
WB SLAVE UNIT tasks
|
===================
|
===================
|
############################################################################*/
|
############################################################################*/
|
|
|
task configure_target ;
|
task configure_target ; //wb_b3_ok
|
input [1:0] beh_dev_num ;
|
input [1:0] beh_dev_num ;
|
reg [31:0] base_address1 ;
|
reg [31:0] base_address1 ;
|
reg [31:0] base_address2 ;
|
reg [31:0] base_address2 ;
|
reg [2:0] Master_ID;
|
reg [2:0] Master_ID;
|
reg [31:0] Target_Config_Addr;
|
reg [31:0] Target_Config_Addr;
|
| Line 1172... |
Line 1183... |
configuration_cycle_write(0, device_num, 0, 1, 0, 4'h3, 32'h0000_0047) ;
|
configuration_cycle_write(0, device_num, 0, 1, 0, 4'h3, 32'h0000_0047) ;
|
|
|
end
|
end
|
endtask //configure_target
|
endtask //configure_target
|
|
|
task test_wb_image ;
|
task test_wb_image ; //wb_b3_ok
|
input [2:0] image_num ;
|
input [2:0] image_num ;
|
reg [11:0] ctrl_offset ;
|
reg [11:0] ctrl_offset ;
|
reg [11:0] ba_offset ;
|
reg [11:0] ba_offset ;
|
reg [11:0] am_offset ;
|
reg [11:0] am_offset ;
|
reg [11:0] ta_offset ;
|
reg [11:0] ta_offset ;
|
| Line 1307... |
Line 1318... |
write_data`WRITE_ADDRESS = target_address ;
|
write_data`WRITE_ADDRESS = target_address ;
|
write_data`WRITE_DATA = wmem_data[0] ;
|
write_data`WRITE_DATA = wmem_data[0] ;
|
write_data`WRITE_SEL = 4'hF ;
|
write_data`WRITE_SEL = 4'hF ;
|
|
|
// handle retries from now on
|
// handle retries from now on
|
write_flags`WB_TRANSFER_AUTO_RTY = 1 ;
|
write_flags`WB_TRANSFER_AUTO_RTY = 0 ;
|
|
|
wishbone_master.wb_single_write( write_data, write_flags, write_status ) ;
|
wishbone_master.wb_single_write( write_data, write_flags, write_status ) ;
|
test_name = "NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCI" ;
|
test_name = "NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCI" ;
|
if ( write_status`CYC_ACTUAL_TRANSFER !== 1 )
|
if ( write_status`CYC_ACTUAL_TRANSFER !== 1 )
|
begin
|
begin
|
| Line 1321... |
Line 1332... |
end
|
end
|
|
|
// read written data back
|
// read written data back
|
read_data`READ_ADDRESS = target_address ;
|
read_data`READ_ADDRESS = target_address ;
|
read_data`READ_SEL = 4'hF ;
|
read_data`READ_SEL = 4'hF ;
|
read_data`READ_TAG_STIM = 0 ;
|
write_flags`WB_TRANSFER_AUTO_RTY = 1'b1 ;
|
wishbone_master.wb_single_read( read_data, write_flags, read_status ) ;
|
wishbone_master.wb_single_read( read_data, write_flags, read_status ) ;
|
if (read_status`CYC_ACTUAL_TRANSFER !== 1)
|
if (read_status`CYC_ACTUAL_TRANSFER !== 1)
|
begin
|
begin
|
$display("Image testing failed! Bridge failed to process single memory read! Time %t ", $time) ;
|
$display("Image testing failed! Bridge failed to process single memory read! Time %t ", $time) ;
|
test_fail("PCI bridge didn't process the read as expected");
|
test_fail("PCI bridge didn't process the read as expected");
|
| Line 1424... |
Line 1435... |
end
|
end
|
|
|
// read written data back
|
// read written data back
|
read_data`READ_ADDRESS = target_address + 4 ;
|
read_data`READ_ADDRESS = target_address + 4 ;
|
read_data`READ_SEL = 4'hF ;
|
read_data`READ_SEL = 4'hF ;
|
read_data`READ_TAG_STIM = 0 ;
|
|
|
|
write_flags`WB_TRANSFER_AUTO_RTY = 1 ;
|
write_flags`WB_TRANSFER_AUTO_RTY = 1 ;
|
|
|
wishbone_master.wb_single_read( read_data, write_flags, read_status ) ;
|
wishbone_master.wb_single_read( read_data, write_flags, read_status ) ;
|
if (read_status`CYC_ACTUAL_TRANSFER !== 1)
|
if (read_status`CYC_ACTUAL_TRANSFER !== 1)
|
| Line 1464... |
Line 1474... |
end
|
end
|
join
|
join
|
|
|
// now do one burst write - length of 6 - minimum depth of fifo is 8, one loc. is always free and one is taken up by address entry
|
// now do one burst write - length of 6 - minimum depth of fifo is 8, one loc. is always free and one is taken up by address entry
|
// prepare write data
|
// prepare write data
|
|
|
for ( i = 0 ; i < 6 ; i = i + 1 )
|
for ( i = 0 ; i < 6 ; i = i + 1 )
|
begin
|
begin
|
write_data`WRITE_DATA = wmem_data[2 + i] ;
|
write_data`WRITE_DATA = wmem_data[2 + i] ;
|
write_data`WRITE_ADDRESS = target_address + 8 + 4*i ;
|
write_data`WRITE_ADDRESS = target_address + 8 + 4*i ;
|
write_data`WRITE_SEL = 4'hF ;
|
write_data`WRITE_SEL = 4'hF ;
|
| Line 1606... |
Line 1617... |
end
|
end
|
join
|
join
|
|
|
read_data`READ_ADDRESS = target_address ;
|
read_data`READ_ADDRESS = target_address ;
|
read_data`READ_SEL = 4'hF ;
|
read_data`READ_SEL = 4'hF ;
|
read_data`READ_TAG_STIM = 0 ;
|
|
|
|
test_name = "SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED" ;
|
test_name = "SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED" ;
|
fork
|
fork
|
begin
|
begin
|
wishbone_master.wb_single_read(read_data, write_flags, read_status) ;
|
wishbone_master.wb_single_read(read_data, write_flags, read_status) ;
|
| Line 1676... |
Line 1686... |
end
|
end
|
join
|
join
|
|
|
read_data`READ_ADDRESS = target_address + 4 ;
|
read_data`READ_ADDRESS = target_address + 4 ;
|
read_data`READ_SEL = 4'hF ;
|
read_data`READ_SEL = 4'hF ;
|
read_data`READ_TAG_STIM = 0 ;
|
|
|
|
test_name = "SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED" ;
|
test_name = "SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED" ;
|
fork
|
fork
|
begin
|
begin
|
wishbone_master.wb_single_read(read_data, write_flags, read_status) ;
|
wishbone_master.wb_single_read(read_data, write_flags, read_status) ;
|
| Line 1746... |
Line 1755... |
end
|
end
|
join
|
join
|
|
|
read_data`READ_ADDRESS = target_address + 8 ;
|
read_data`READ_ADDRESS = target_address + 8 ;
|
read_data`READ_SEL = 4'hF ;
|
read_data`READ_SEL = 4'hF ;
|
read_data`READ_TAG_STIM = 0 ;
|
|
|
|
test_name = "SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED" ;
|
test_name = "SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED" ;
|
fork
|
fork
|
begin
|
begin
|
wishbone_master.wb_single_read(read_data, write_flags, read_status) ;
|
wishbone_master.wb_single_read(read_data, write_flags, read_status) ;
|
| Line 1788... |
Line 1796... |
|
|
write_data`WRITE_ADDRESS = target_address ;
|
write_data`WRITE_ADDRESS = target_address ;
|
write_data`WRITE_DATA = wmem_data[11] ;
|
write_data`WRITE_DATA = wmem_data[11] ;
|
write_data`WRITE_SEL = 4'hF ;
|
write_data`WRITE_SEL = 4'hF ;
|
|
|
// handle retries from now on
|
// don't handle retries from now on
|
write_flags`WB_TRANSFER_AUTO_RTY = 0 ;
|
write_flags`WB_TRANSFER_AUTO_RTY = 0 ;
|
|
|
test_name = "I/O WRITE TRANSACTION FROM WB TO PCI TEST" ;
|
test_name = "I/O WRITE TRANSACTION FROM WB TO PCI TEST" ;
|
fork
|
fork
|
begin
|
begin
|
| Line 1814... |
Line 1822... |
end
|
end
|
join
|
join
|
|
|
read_data`READ_ADDRESS = target_address ;
|
read_data`READ_ADDRESS = target_address ;
|
read_data`READ_SEL = 4'hF ;
|
read_data`READ_SEL = 4'hF ;
|
read_data`READ_TAG_STIM = 0 ;
|
|
|
|
write_flags`WB_TRANSFER_AUTO_RTY = 1 ;
|
write_flags`WB_TRANSFER_AUTO_RTY = 1 ;
|
|
|
// currently io commands are not supported by behavioral target - transfer should not be completed
|
// currently io commands are not supported by behavioral target - transfer should not be completed
|
test_name = "I/O READ TRANSACTION FROM WB TO PCI TEST" ;
|
test_name = "I/O READ TRANSACTION FROM WB TO PCI TEST" ;
|
| Line 1958... |
Line 1965... |
end
|
end
|
|
|
end //main
|
end //main
|
endtask //test_wb_image
|
endtask //test_wb_image
|
|
|
task wb_slave_errors ;
|
task wb_slave_errors ; //wb_b3_ok
|
reg [11:0] ctrl_offset ;
|
reg [11:0] ctrl_offset ;
|
reg [11:0] ba_offset ;
|
reg [11:0] ba_offset ;
|
reg [11:0] am_offset ;
|
reg [11:0] am_offset ;
|
reg [11:0] ta_offset ;
|
reg [11:0] ta_offset ;
|
reg `WRITE_STIM_TYPE write_data ;
|
reg `WRITE_STIM_TYPE write_data ;
|
| Line 2102... |
Line 2109... |
// perform same tests for read accesses
|
// perform same tests for read accesses
|
test_name = "SINGLE ERRONEOUS MEMORY READ TO WB SLAVE" ;
|
test_name = "SINGLE ERRONEOUS MEMORY READ TO WB SLAVE" ;
|
|
|
read_data`READ_ADDRESS = target_address + 2 ;
|
read_data`READ_ADDRESS = target_address + 2 ;
|
read_data`READ_SEL = 4'hF ;
|
read_data`READ_SEL = 4'hF ;
|
read_data`READ_TAG_STIM = 0 ;
|
|
|
|
wishbone_master.wb_single_read( read_data, write_flags, read_status ) ;
|
wishbone_master.wb_single_read( read_data, write_flags, read_status ) ;
|
if ( (read_status`CYC_ACTUAL_TRANSFER !== 0) || (read_status`CYC_ERR !== 1) )
|
if ( (read_status`CYC_ACTUAL_TRANSFER !== 0) || (read_status`CYC_ERR !== 1) )
|
begin
|
begin
|
$display("WISHBONE slave error termination testing failed! WB Slave didn't signal error on access to non-alligned memory address! Time %t ", $time) ;
|
$display("WISHBONE slave error termination testing failed! WB Slave didn't signal error on access to non-alligned memory address! Time %t ", $time) ;
|
| Line 2142... |
Line 2148... |
disable no_transaction ;
|
disable no_transaction ;
|
disable main ;
|
disable main ;
|
end
|
end
|
|
|
// prepare read data
|
// prepare read data
|
|
|
for ( i = 0 ; i < 6 ; i = i + 1 )
|
for ( i = 0 ; i < 6 ; i = i + 1 )
|
begin
|
begin
|
read_data`READ_ADDRESS = target_address + 4*i + 3 ;
|
read_data`READ_ADDRESS = target_address + 4*i + 3 ;
|
read_data`READ_SEL = 4'hF ;
|
read_data`READ_SEL = 4'hF ;
|
wishbone_master.blk_read_data_in[i] = read_data ;
|
wishbone_master.blk_read_data_in[i] = read_data ;
|
| Line 2217... |
Line 2224... |
disable no_transaction ;
|
disable no_transaction ;
|
disable main ;
|
disable main ;
|
end
|
end
|
|
|
write_data`WRITE_SEL = 4'b1100 ;
|
write_data`WRITE_SEL = 4'b1100 ;
|
|
|
wishbone_master.wb_single_write( write_data, write_flags, write_status ) ;
|
wishbone_master.wb_single_write( write_data, write_flags, write_status ) ;
|
if ( (write_status`CYC_ACTUAL_TRANSFER !== 0) || (write_status`CYC_ERR !== 1) )
|
if ( (write_status`CYC_ACTUAL_TRANSFER !== 0) || (write_status`CYC_ERR !== 1) )
|
begin
|
begin
|
$display("WISHBONE slave error termination testing failed! WB Slave didn't signal error on erroneous access to IO mapped address! Time %t ", $time) ;
|
$display("WISHBONE slave error termination testing failed! WB Slave didn't signal error on erroneous access to IO mapped address! Time %t ", $time) ;
|
$display("ADDRESS : %h, SEL : %b ", write_data`WRITE_ADDRESS, write_data`WRITE_SEL) ;
|
$display("ADDRESS : %h, SEL : %b ", write_data`WRITE_ADDRESS, write_data`WRITE_SEL) ;
|
| Line 2289... |
Line 2295... |
|
|
test_name = "ERRONEOUS I/O READ TO WB SLAVE" ;
|
test_name = "ERRONEOUS I/O READ TO WB SLAVE" ;
|
|
|
read_data`READ_ADDRESS = target_address + 3 ;
|
read_data`READ_ADDRESS = target_address + 3 ;
|
read_data`READ_SEL = 4'hF ;
|
read_data`READ_SEL = 4'hF ;
|
read_data`READ_TAG_STIM = 0 ;
|
|
|
|
wishbone_master.wb_single_read( read_data, write_flags, read_status ) ;
|
wishbone_master.wb_single_read( read_data, write_flags, read_status ) ;
|
if ( (read_status`CYC_ACTUAL_TRANSFER !== 0) || (read_status`CYC_ERR !== 1) )
|
if ( (read_status`CYC_ACTUAL_TRANSFER !== 0) || (read_status`CYC_ERR !== 1) )
|
begin
|
begin
|
$display("WISHBONE slave error termination testing failed! WB Slave didn't signal error on erroneous access to IO mapped address! Time %t ", $time) ;
|
$display("WISHBONE slave error termination testing failed! WB Slave didn't signal error on erroneous access to IO mapped address! Time %t ", $time) ;
|
| Line 2305... |
Line 2310... |
end
|
end
|
|
|
test_ok ;
|
test_ok ;
|
|
|
test_name = "CAB I/O WRITE TO WB SLAVE" ;
|
test_name = "CAB I/O WRITE TO WB SLAVE" ;
|
|
|
// prepare write data
|
// prepare write data
|
for ( i = 0 ; i < 6 ; i = i + 1 )
|
for ( i = 0 ; i < 6 ; i = i + 1 )
|
begin
|
begin
|
write_data`WRITE_DATA = wmem_data[i] ;
|
write_data`WRITE_DATA = wmem_data[i] ;
|
write_data`WRITE_ADDRESS = target_address + 4*i ;
|
write_data`WRITE_ADDRESS = target_address + 4*i ;
|
| Line 2332... |
Line 2338... |
end
|
end
|
|
|
test_ok ;
|
test_ok ;
|
|
|
test_name = "CAB I/O READ TO WB SLAVE" ;
|
test_name = "CAB I/O READ TO WB SLAVE" ;
|
|
|
// prepare read data
|
// prepare read data
|
for ( i = 0 ; i < 6 ; i = i + 1 )
|
for ( i = 0 ; i < 6 ; i = i + 1 )
|
begin
|
begin
|
read_data`READ_ADDRESS = target_address + 4*i ;
|
read_data`READ_ADDRESS = target_address + 4*i ;
|
read_data`READ_SEL = 4'hF ;
|
read_data`READ_SEL = 4'hF ;
|
| Line 2357... |
Line 2364... |
|
|
$display("**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************") ;
|
$display("**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************") ;
|
|
|
$display("************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************") ;
|
$display("************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************") ;
|
|
|
|
begin:test_erroneous_config_access_blk
|
|
reg do_write_test ;
|
|
reg do_read_test ;
|
|
|
target_address = {`WB_CONFIGURATION_BASE, 12'h0} ;
|
target_address = {`WB_CONFIGURATION_BASE, 12'h0} ;
|
write_data`WRITE_ADDRESS = target_address + 1 ;
|
|
write_data`WRITE_DATA = wmem_data[0] ;
|
|
write_data`WRITE_SEL = 4'hF ;
|
|
|
|
// don't handle retries
|
do_write_test = 1'b0 ;
|
write_flags`WB_TRANSFER_AUTO_RTY = 0 ;
|
do_read_test = 1'b0 ;
|
|
|
`ifdef HOST
|
`ifdef HOST
|
`define DO_W_CONF_TEST
|
|
`define DO_R_CONF_TEST
|
do_write_test = 1'b1 ;
|
|
do_read_test = 1'b1 ;
|
|
|
`else
|
`else
|
|
|
`ifdef WB_CNF_IMAGE
|
`ifdef WB_CNF_IMAGE
|
`define DO_R_CONF_TEST
|
|
|
do_read_test = 1'b1 ;
|
|
|
`endif
|
`endif
|
|
|
`endif
|
`endif
|
|
|
`ifdef DO_W_CONF_TEST
|
`ifdef PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS
|
|
`else
|
|
|
|
if (do_write_test)
|
|
begin
|
|
|
|
write_data`WRITE_ADDRESS = target_address + 1 ;
|
|
write_data`WRITE_DATA = wmem_data[0] ;
|
|
write_data`WRITE_SEL = 4'hF ;
|
|
|
|
// don't handle retries
|
|
write_flags`WB_TRANSFER_AUTO_RTY = 0 ;
|
|
|
test_name = "ERRONEOUS WB CONFIGURATION WRITE ACCESS" ;
|
test_name = "ERRONEOUS WB CONFIGURATION WRITE ACCESS" ;
|
wishbone_master.wb_single_write( write_data, write_flags, write_status ) ;
|
wishbone_master.wb_single_write( write_data, write_flags, write_status ) ;
|
if ( (write_status`CYC_ACTUAL_TRANSFER !== 0) || (write_status`CYC_ERR !== 1) )
|
if ( (write_status`CYC_ACTUAL_TRANSFER !== 0) || (write_status`CYC_ERR !== 1) )
|
begin
|
begin
|
$display("WISHBONE slave error termination testing failed! WB Slave didn't signal error on access to non-alligned configuration address! Time %t ", $time) ;
|
$display("WISHBONE slave error termination testing failed! WB Slave didn't signal error on access to non-alligned configuration address! Time %t ", $time) ;
|
| Line 2386... |
Line 2412... |
test_fail("WB Slave state machine didn't reject erroneous Configuration write as expected") ;
|
test_fail("WB Slave state machine didn't reject erroneous Configuration write as expected") ;
|
disable no_transaction ;
|
disable no_transaction ;
|
disable main ;
|
disable main ;
|
end
|
end
|
|
|
write_data`WRITE_ADDRESS = target_address + 2 ;
|
// try write to configuration cycle address register with non alligned address
|
|
write_data`WRITE_ADDRESS = target_address + {4'h1, `CNF_ADDR_ADDR, 2'b10} ;
|
|
|
wishbone_master.wb_single_write( write_data, write_flags, write_status ) ;
|
wishbone_master.wb_single_write( write_data, write_flags, write_status ) ;
|
if ( (write_status`CYC_ACTUAL_TRANSFER !== 0) || (write_status`CYC_ERR !== 1) )
|
if ( (write_status`CYC_ACTUAL_TRANSFER !== 0) || (write_status`CYC_ERR !== 1) )
|
begin
|
begin
|
$display("WISHBONE slave error termination testing failed! WB Slave didn't signal error on access to non-alligned configuration address! Time %t ", $time) ;
|
$display("WISHBONE slave error termination testing failed! WB Slave didn't signal error on access to non-alligned configuration address! Time %t ", $time) ;
|
| Line 2398... |
Line 2425... |
test_fail("WB Slave state machine didn't reject erroneous Configuration write as expected") ;
|
test_fail("WB Slave state machine didn't reject erroneous Configuration write as expected") ;
|
disable no_transaction ;
|
disable no_transaction ;
|
disable main ;
|
disable main ;
|
end
|
end
|
|
|
write_data`WRITE_ADDRESS = target_address + 3 ;
|
write_data`WRITE_ADDRESS = target_address + {4'h1, `CNF_DATA_ADDR, 2'b11} ;
|
|
|
|
// try write to configuration cycle data register with non alligned address
|
wishbone_master.wb_single_write( write_data, write_flags, write_status ) ;
|
wishbone_master.wb_single_write( write_data, write_flags, write_status ) ;
|
if ( (write_status`CYC_ACTUAL_TRANSFER !== 0) || (write_status`CYC_ERR !== 1) )
|
if ( (write_status`CYC_ACTUAL_TRANSFER !== 0) || (write_status`CYC_ERR !== 1) )
|
begin
|
begin
|
$display("WISHBONE slave error termination testing failed! WB Slave didn't signal error on access to non-alligned configuration address! Time %t ", $time) ;
|
$display("WISHBONE slave error termination testing failed! WB Slave didn't signal error on access to non-alligned configuration address! Time %t ", $time) ;
|
$display("WISHBONE slave response: ACK = %b, RTY = %b, ERR = %b ", write_status`CYC_ACK, write_status`CYC_RTY, write_status`CYC_ERR) ;
|
$display("WISHBONE slave response: ACK = %b, RTY = %b, ERR = %b ", write_status`CYC_ACK, write_status`CYC_RTY, write_status`CYC_ERR) ;
|
| Line 2411... |
Line 2439... |
disable no_transaction ;
|
disable no_transaction ;
|
disable main ;
|
disable main ;
|
end
|
end
|
|
|
test_ok ;
|
test_ok ;
|
`endif
|
end
|
|
|
`ifdef DO_R_CONF_TEST
|
if (do_read_test)
|
|
begin
|
test_name = "ERRONEOUS WB CONFIGURATION READ ACCESS" ;
|
test_name = "ERRONEOUS WB CONFIGURATION READ ACCESS" ;
|
read_data`READ_ADDRESS = target_address + 3 ;
|
// try read from configuration cycle data register with non alligned address
|
|
read_data`READ_ADDRESS = target_address + {4'h1, `CNF_DATA_ADDR, 2'b01} ;
|
read_data`READ_SEL = 4'hF ;
|
read_data`READ_SEL = 4'hF ;
|
read_data`READ_TAG_STIM = 0 ;
|
|
|
|
wishbone_master.wb_single_read( read_data, write_flags, read_status ) ;
|
wishbone_master.wb_single_read( read_data, write_flags, read_status ) ;
|
if ( (read_status`CYC_ACTUAL_TRANSFER !== 0) || (read_status`CYC_ERR !== 1) )
|
if ( (read_status`CYC_ACTUAL_TRANSFER !== 0) || (read_status`CYC_ERR !== 1) )
|
begin
|
begin
|
$display("WISHBONE slave error termination testing failed! WB Slave didn't signal error on access to non-alligned configuration address! Time %t ", $time) ;
|
$display("WISHBONE slave error termination testing failed! WB Slave didn't signal error on access to non-alligned configuration address! Time %t ", $time) ;
|
| Line 2430... |
Line 2459... |
disable no_transaction ;
|
disable no_transaction ;
|
disable main ;
|
disable main ;
|
end
|
end
|
|
|
test_ok ;
|
test_ok ;
|
|
end
|
|
|
`endif
|
`endif
|
|
|
`ifdef DO_W_CONF_TEST
|
if (do_write_test)
|
|
begin
|
// prepare write data
|
// prepare write data
|
test_name = "WB CAB CONFIGURATION WRITE ACCESS" ;
|
test_name = "WB CAB CONFIGURATION WRITE ACCESS" ;
|
|
|
for ( i = 0 ; i < 6 ; i = i + 1 )
|
for ( i = 0 ; i < 6 ; i = i + 1 )
|
begin
|
begin
|
write_data`WRITE_DATA = wmem_data[i] ;
|
write_data`WRITE_DATA = wmem_data[i] ;
|
write_data`WRITE_ADDRESS = target_address + 4*i ;
|
write_data`WRITE_ADDRESS = target_address + 4*i + {4'h1, `CNF_DATA_ADDR, 2'b00};
|
write_data`WRITE_SEL = 4'hF ;
|
write_data`WRITE_SEL = 4'hF ;
|
wishbone_master.blk_write_data[i] = write_data ;
|
wishbone_master.blk_write_data[i] = write_data ;
|
end
|
end
|
|
|
write_flags`WB_TRANSFER_AUTO_RTY = 0 ;
|
write_flags`WB_TRANSFER_AUTO_RTY = 0 ;
|
| Line 2458... |
Line 2491... |
test_fail("WB Slave state machine didn't reject CAB Configuration write as expected") ;
|
test_fail("WB Slave state machine didn't reject CAB Configuration write as expected") ;
|
disable no_transaction ;
|
disable no_transaction ;
|
disable main ;
|
disable main ;
|
end
|
end
|
test_ok ;
|
test_ok ;
|
`endif
|
end
|
|
|
`ifdef DO_R_CONF_TEST
|
if (do_read_test)
|
|
begin
|
// prepare read data
|
// prepare read data
|
test_name = "WB CAB CONFIGURATION READ ACCESS" ;
|
test_name = "WB CAB CONFIGURATION READ ACCESS" ;
|
|
|
for ( i = 0 ; i < 6 ; i = i + 1 )
|
for ( i = 0 ; i < 6 ; i = i + 1 )
|
begin
|
begin
|
read_data`READ_ADDRESS = target_address + 4*i ;
|
read_data`READ_ADDRESS = target_address + 4*i + {4'h1, `CNF_DATA_ADDR, 2'b00};
|
read_data`READ_SEL = 4'hF ;
|
read_data`READ_SEL = 4'hF ;
|
wishbone_master.blk_read_data_in[i] = read_data ;
|
wishbone_master.blk_read_data_in[i] = read_data ;
|
end
|
end
|
|
|
wishbone_master.wb_block_read(write_flags, read_status) ;
|
wishbone_master.wb_block_read(write_flags, read_status) ;
|
| Line 2481... |
Line 2516... |
test_fail("WB Slave state machine didn't reject CAB Configuration read as expected") ;
|
test_fail("WB Slave state machine didn't reject CAB Configuration read as expected") ;
|
disable no_transaction ;
|
disable no_transaction ;
|
disable main ;
|
disable main ;
|
end
|
end
|
test_ok ;
|
test_ok ;
|
`endif
|
end
|
|
|
`ifdef GUEST
|
`ifdef GUEST
|
skip = 1 ;
|
skip = 1 ;
|
`endif
|
`endif
|
|
end // test_erroneous_config_access_blk
|
|
|
// disable image
|
// disable image
|
test_name = "DISABLE IMAGE" ;
|
test_name = "DISABLE IMAGE" ;
|
config_write( am_offset, 32'h7FFF_FFFF, 4'hF, ok ) ;
|
config_write( am_offset, 32'h7FFF_FFFF, 4'hF, ok ) ;
|
if ( ok !== 1 )
|
if ( ok !== 1 )
|
| Line 2684... |
Line 2720... |
|
|
// read data from second write
|
// read data from second write
|
write_flags`WB_TRANSFER_AUTO_RTY = 1 ;
|
write_flags`WB_TRANSFER_AUTO_RTY = 1 ;
|
read_data`READ_ADDRESS = target_address ;
|
read_data`READ_ADDRESS = target_address ;
|
read_data`READ_SEL = 4'hF ;
|
read_data`READ_SEL = 4'hF ;
|
read_data`READ_TAG_STIM = 0 ;
|
|
|
|
wishbone_master.wb_single_read( read_data, write_flags, read_status ) ;
|
wishbone_master.wb_single_read( read_data, write_flags, read_status ) ;
|
|
|
if ( read_status`READ_DATA !== wmem_data[101] )
|
if ( read_status`READ_DATA !== wmem_data[101] )
|
begin
|
begin
|
| Line 3157... |
Line 3192... |
0, // type of configuration cycle
|
0, // type of configuration cycle
|
4'b0001, // byte enables
|
4'b0001, // byte enables
|
32'h0000_0000 // data
|
32'h0000_0000 // data
|
) ;
|
) ;
|
|
|
|
|
for ( i = 0 ; i < 3 ; i = i + 1 )
|
for ( i = 0 ; i < 3 ; i = i + 1 )
|
begin
|
begin
|
read_data`READ_ADDRESS = target_address + 4*i ;
|
read_data`READ_ADDRESS = target_address + 4*i ;
|
read_data`READ_SEL = 4'hF ;
|
read_data`READ_SEL = 4'hF ;
|
wishbone_master.blk_read_data_in[i] = read_data ;
|
wishbone_master.blk_read_data_in[i] = read_data ;
|
| Line 3459... |
Line 3495... |
if ( temp_val1[31:24] !== {4'b0101, `BC_MEM_WRITE} )
|
if ( temp_val1[31:24] !== {4'b0101, `BC_MEM_WRITE} )
|
begin
|
begin
|
$display("PCI bus error handling testing failed! Time %t ", $time) ;
|
$display("PCI bus error handling testing failed! Time %t ", $time) ;
|
$display("Value in W_ERR_CS register was wrong!") ;
|
$display("Value in W_ERR_CS register was wrong!") ;
|
$display("Expected BE = %b, BC = %b ; actuals: BE = %b, BC = %b ", 4'b0101, `BC_MEM_WRITE, temp_val1[31:28], temp_val1[27:24]) ;
|
$display("Expected BE = %b, BC = %b ; actuals: BE = %b, BC = %b ", 4'b0101, `BC_MEM_WRITE, temp_val1[31:28], temp_val1[27:24]) ;
|
test_fail("BE Field didn't provided expected value") ;
|
test_fail("BE Field didn't provide expected value") ;
|
ok = 0 ;
|
ok = 0 ;
|
end
|
end
|
|
|
if ( ok )
|
if ( ok )
|
test_ok ;
|
test_ok ;
|
| Line 3480... |
Line 3516... |
test_fail("Value in WB Erroneous Address register was wrong") ;
|
test_fail("Value in WB Erroneous Address register was wrong") ;
|
ok = 0 ;
|
ok = 0 ;
|
end
|
end
|
|
|
config_read( { 4'h1, `W_ERR_DATA_ADDR, 2'b00}, 4'hF, temp_val1 ) ;
|
config_read( { 4'h1, `W_ERR_DATA_ADDR, 2'b00}, 4'hF, temp_val1 ) ;
|
if ( temp_val1 !== wmem_data[120] )
|
|
|
// mask expected and actual values, since all byte enables were not active
|
|
if ( (temp_val1 & 32'hff_00_ff_00) !== (wmem_data[120] & 32'hff_00_ff_00) )
|
begin
|
begin
|
$display("PCI bus error handling testing failed! Time %t ", $time) ;
|
$display("PCI bus error handling testing failed! Time %t ", $time) ;
|
$display("Value in W_ERR_DATA register was wrong!") ;
|
$display("Value in W_ERR_DATA register was wrong!") ;
|
$display("Expected value = %h, actual value = %h " , wmem_data[120], temp_val1 ) ;
|
$display("Expected value = %h, actual value = %h " , wmem_data[120] & 32'hff_00_ff_00, temp_val1 & 32'hff_00_ff_00) ;
|
test_fail("Value in WB Erroneous Data register was wrong") ;
|
test_fail("Value in WB Erroneous Data register was wrong") ;
|
ok = 0 ;
|
ok = 0 ;
|
end
|
end
|
|
|
if ( ok )
|
if ( ok )
|
| Line 3598... |
Line 3636... |
|
|
if ( temp_val1[31:24] !== {4'b0101, `BC_MEM_WRITE} )
|
if ( temp_val1[31:24] !== {4'b0101, `BC_MEM_WRITE} )
|
begin
|
begin
|
$display("PCI bus error handling testing failed! Time %t ", $time) ;
|
$display("PCI bus error handling testing failed! Time %t ", $time) ;
|
$display("Value in W_ERR_CS register was wrong!") ;
|
$display("Value in W_ERR_CS register was wrong!") ;
|
$display("Expected BE = %b, BC = %b ; actuals: BE = %b, BC = %b ", 4'b1010, `BC_MEM_WRITE, temp_val1[31:28], temp_val1[27:24]) ;
|
$display("Expected BE = %b, BC = %b ; actuals: BE = %b, BC = %b ", 4'b0101, `BC_MEM_WRITE, temp_val1[31:28], temp_val1[27:24]) ;
|
test_fail("BE or bus command field(s) didn't provide expected value") ;
|
test_fail("BE or bus command field(s) didn't provide expected value") ;
|
ok = 0 ;
|
ok = 0 ;
|
end
|
end
|
|
|
if ( ok )
|
if ( ok )
|
| Line 3621... |
Line 3659... |
ok = 0 ;
|
ok = 0 ;
|
|
|
end
|
end
|
|
|
config_read( { 4'h1, `W_ERR_DATA_ADDR, 2'b00}, 4'hF, temp_val1 ) ;
|
config_read( { 4'h1, `W_ERR_DATA_ADDR, 2'b00}, 4'hF, temp_val1 ) ;
|
if ( temp_val1 !== wmem_data[121] )
|
if ( (temp_val1 & 32'hFF_00_FF_00) !== (wmem_data[121] & 32'hFF_00_FF_00) )
|
begin
|
begin
|
$display("PCI bus error handling testing failed! Time %t ", $time) ;
|
$display("PCI bus error handling testing failed! Time %t ", $time) ;
|
$display("Value in W_ERR_DATA register was wrong!") ;
|
$display("Value in W_ERR_DATA register was wrong!") ;
|
$display("Expected value = %h, actual value = %h " , wmem_data[121], temp_val1 ) ;
|
$display("Expected value = %h, actual value = %h " , wmem_data[121] & 32'hFF_00_FF_00, temp_val1 & 32'hFF_00_FF_00) ;
|
test_fail("Value in WB Erroneous Data register was wrong") ;
|
test_fail("Value in WB Erroneous Data register was wrong") ;
|
ok = 0 ;
|
ok = 0 ;
|
end
|
end
|
|
|
if ( ok )
|
if ( ok )
|
| Line 4065... |
Line 4103... |
test_fail("WB Erroneous Address register didn't provide right value") ;
|
test_fail("WB Erroneous Address register didn't provide right value") ;
|
ok = 0 ;
|
ok = 0 ;
|
end
|
end
|
|
|
config_read( { 4'h1, `W_ERR_DATA_ADDR, 2'b00}, 4'hF, temp_val1 ) ;
|
config_read( { 4'h1, `W_ERR_DATA_ADDR, 2'b00}, 4'hF, temp_val1 ) ;
|
if ( temp_val1 !== 32'hAAAA_AAAA )
|
if ( (temp_val1 & 32'h00_ff_00_ff) !== 32'h00AA_00AA )
|
begin
|
begin
|
$display("PCI bus error handling testing failed! Time %t ", $time) ;
|
$display("PCI bus error handling testing failed! Time %t ", $time) ;
|
$display("Value in W_ERR_DATA register was wrong!") ;
|
$display("Value in W_ERR_DATA register was wrong!") ;
|
$display("Expected value = %h, actual value = %h " , 32'hAAAA_AAAA, temp_val1 ) ;
|
$display("Expected value = %h, actual value = %h " , 32'h00AA_00AA, temp_val1 & 32'h00_ff_00_ff) ;
|
test_fail("WB Erroneous Data register didn't provide right value") ;
|
test_fail("WB Erroneous Data register didn't provide right value") ;
|
ok = 0 ;
|
ok = 0 ;
|
end
|
end
|
|
|
if ( ok )
|
if ( ok )
|
| Line 4507... |
Line 4545... |
$display(" Introducing Parity Errors to Master reads ! " ) ;
|
$display(" Introducing Parity Errors to Master reads ! " ) ;
|
|
|
read_data = 0 ;
|
read_data = 0 ;
|
read_data`READ_ADDRESS = target_address ;
|
read_data`READ_ADDRESS = target_address ;
|
read_data`READ_SEL = 4'hF ;
|
read_data`READ_SEL = 4'hF ;
|
read_data`READ_TAG_STIM = 0 ;
|
|
|
|
write_flags`WB_TRANSFER_AUTO_RTY = 1 ;
|
write_flags`WB_TRANSFER_AUTO_RTY = 1 ;
|
|
|
// enable parity and system error interrupts
|
// enable parity and system error interrupts
|
config_write ( icr_offset, 32'h0000_0018, 4'h1, ok ) ;
|
config_write ( icr_offset, 32'h0000_0018, 4'h1, ok ) ;
|
| Line 7692... |
Line 7729... |
$display("Bridge failed to process CAB write!") ;
|
$display("Bridge failed to process CAB write!") ;
|
test_fail("bridge didn't post whole burst memory write") ;
|
test_fail("bridge didn't post whole burst memory write") ;
|
disable main ;
|
disable main ;
|
end
|
end
|
end
|
end
|
begin
|
begin:cab_master_write_interrupted_by_latency_timeout2
|
|
reg [31:0] ret_adr ; reg [3:0] ret_bc ; reg ret_gnt_deasserted ;
|
|
integer ret_num_of_transfers ; integer ret_num_of_cycles ;
|
|
|
|
ok = 1'b1 ;
|
|
|
// wait for bridge's master to start transaction
|
// wait for bridge's master to start transaction
|
@(posedge pci_clock) ;
|
monitor32.get_pci_op(ret_adr, ret_bc) ;
|
while ( FRAME === 1 )
|
|
@(posedge pci_clock) ;
|
|
|
|
// start behavioral master request
|
if (ret_adr !== target_address)
|
PCIU_MEM_WRITE("MEM_WRITE ", `Test_Master_1,
|
begin
|
target_address, wmem_data[1023], `Test_All_Bytes,
|
$display("%m detected an error!") ;
|
1, 8'h2_0, `Test_One_Zero_Target_WS,
|
test_fail("invalid address was detected when PCI Master initiated a burst write operation") ;
|
`Test_Devsel_Medium, `Test_Target_Normal_Completion);
|
ok = 0 ;
|
|
end
|
|
|
do_pause ( 1 ) ;
|
if (ret_bc !== `BC_MEM_WRITE)
|
|
begin
|
|
$display("%m detected an error!") ;
|
|
test_fail("invalid bus command was detected when PCI Master should initiate a burst write operation") ;
|
|
ok = 0 ;
|
end
|
end
|
|
|
|
// remove the grant from PCI Bridge
|
|
tc_gnt_allow = 1'b1 ;
|
|
|
|
fork
|
begin
|
begin
|
pci_transaction_progress_monitor( target_address, `BC_MEM_WRITE, 0, 2, 1'b0, 1'b1, 0, ok ) ;
|
monitor32.get_pci_op_num_of_transfers(ret_num_of_transfers, ret_gnt_deasserted) ;
|
if ( ok !== 1 )
|
end
|
test_fail("bridge didn't finish the burst write transaction after latency timer has expired") ;
|
begin
|
|
monitor32.get_pci_op_num_of_cycles(ret_num_of_cycles) ;
|
|
end
|
|
join
|
|
|
|
// put arbiter back into the control of the grant line
|
|
tc_gnt_allow = 1'b0 ;
|
|
|
|
// check number of cycles bridge kept the frame asserted!
|
|
if (ret_gnt_deasserted !== 1'b1)
|
|
begin
|
|
$display("%m detected an error!") ;
|
|
test_fail("GNT line wasn't deasserted during latency timer operation tests") ;
|
|
ok = 0 ;
|
|
end
|
else
|
else
|
|
begin
|
|
if (ret_num_of_cycles > 2)
|
|
begin
|
|
$display("%m detected an error!") ;
|
|
test_fail("PCI Master was expected to deassert FRAME after two cycles and it didn't do that!") ;
|
|
ok = 0 ;
|
|
end
|
|
end
|
|
|
|
if (ret_num_of_transfers !== 2)
|
|
begin
|
|
$display("%m detected an error!") ;
|
|
test_fail("PCI Master must didn't transfer 2 words in a burst, latency timer was set to a value of 2 and timeout occured") ;
|
|
ok = 0 ;
|
|
end
|
|
|
|
// now check the remainder of the transaction!
|
|
if (ok === 1'b1)
|
|
begin
|
|
pci_transaction_progress_monitor(target_address + 4 * ret_num_of_transfers, `BC_MEM_WRITE, 6 - ret_num_of_transfers, 0, 1'b1, 1'b0, 0, ok) ;
|
|
if (ok !== 1'b1)
|
|
begin
|
|
$display("%m detected an error!") ;
|
|
test_fail("PCI Master did invalid transaction on PCI bus") ;
|
|
ok = 0 ;
|
|
end
|
|
end
|
|
|
|
if (ok === 1'b1)
|
test_ok ;
|
test_ok ;
|
end
|
end
|
join
|
join
|
|
|
// perform a read to check data
|
// perform a read to check data
|
| Line 7728... |
Line 7821... |
|
|
write_flags`WB_TRANSFER_SIZE = 6 ;
|
write_flags`WB_TRANSFER_SIZE = 6 ;
|
write_flags`WB_TRANSFER_AUTO_RTY = 1 ;
|
write_flags`WB_TRANSFER_AUTO_RTY = 1 ;
|
write_flags`WB_TRANSFER_CAB = 1 ;
|
write_flags`WB_TRANSFER_CAB = 1 ;
|
|
|
test_name = "BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUT" ;
|
test_name = "CHECK VALUES OF BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUT" ;
|
wishbone_master.wb_block_read( write_flags, read_status ) ;
|
wishbone_master.wb_block_read( write_flags, read_status ) ;
|
|
|
if ( read_status`CYC_ACTUAL_TRANSFER !== 6 )
|
if ( read_status`CYC_ACTUAL_TRANSFER !== 6 )
|
begin
|
begin
|
$display("Transaction progress testing failed! Time %t ", $time) ;
|
$display("Transaction progress testing failed! Time %t ", $time) ;
|
| Line 7772... |
Line 7865... |
$display("Bridge failed to process CAB read!") ;
|
$display("Bridge failed to process CAB read!") ;
|
test_fail("bridge didn't process burst read as expected") ;
|
test_fail("bridge didn't process burst read as expected") ;
|
ok = 0 ;
|
ok = 0 ;
|
end
|
end
|
end
|
end
|
begin
|
begin:cab_memory_read_interrupted_by_latency_timeout2
|
|
reg [31:0] ret_adr ; reg [3:0] ret_bc ; reg ret_gnt_deasserted ;
|
|
integer ret_num_of_transfers ; integer ret_num_of_cycles ;
|
|
|
|
ok = 1'b1 ;
|
|
|
// wait for bridge's master to start transaction
|
// wait for bridge's master to start transaction
|
@(posedge pci_clock) ;
|
monitor32.get_pci_op(ret_adr, ret_bc) ;
|
while ( FRAME === 1 )
|
|
@(posedge pci_clock) ;
|
|
|
|
// start behavioral master request
|
if (ret_adr !== target_address)
|
PCIU_MEM_WRITE("MEM_WRITE ", `Test_Master_1,
|
begin
|
target_address, wmem_data[0], `Test_All_Bytes,
|
$display("%m detected an error!") ;
|
1, 8'h3_0, `Test_One_Zero_Target_WS,
|
test_fail("invalid address was detected when PCI Master initiated a burst read operation") ;
|
`Test_Devsel_Medium, `Test_Target_Normal_Completion);
|
ok = 0 ;
|
|
end
|
|
|
do_pause ( 1 ) ;
|
if (ret_bc !== `BC_MEM_READ_MUL)
|
|
begin
|
|
$display("%m detected an error!") ;
|
|
test_fail("invalid bus command was detected when PCI Master should initiate a burst read operation") ;
|
|
ok = 0 ;
|
end
|
end
|
|
|
|
// remove the grant from PCI Bridge
|
|
tc_gnt_allow = 1'b1 ;
|
|
|
|
fork
|
begin
|
begin
|
pci_transaction_progress_monitor( target_address, `BC_MEM_READ_MUL, 0, 2, 1'b0, 1'b1, 0, ok ) ;
|
monitor32.get_pci_op_num_of_transfers(ret_num_of_transfers, ret_gnt_deasserted) ;
|
if ( ok !== 1 )
|
end
|
test_fail("bridge did invalid memory read transaction or none at all or behavioral target didn't respond as expected") ;
|
begin
|
|
monitor32.get_pci_op_num_of_cycles(ret_num_of_cycles) ;
|
|
end
|
|
join
|
|
|
|
// put arbiter back into the control of the grant line
|
|
tc_gnt_allow = 1'b0 ;
|
|
|
|
// check number of cycles bridge kept the frame asserted!
|
|
if (ret_gnt_deasserted !== 1'b1)
|
|
begin
|
|
$display("%m detected an error!") ;
|
|
test_fail("GNT line wasn't deasserted during latency timer operation tests") ;
|
|
ok = 0 ;
|
|
end
|
|
else
|
|
begin
|
|
if (ret_num_of_cycles > 2)
|
|
begin
|
|
$display("%m detected an error!") ;
|
|
test_fail("PCI Master was expected to deassert FRAME after two cycles and it didn't do that!") ;
|
|
ok = 0 ;
|
|
end
|
|
end
|
|
|
|
if (ret_num_of_transfers !== 2)
|
|
begin
|
|
$display("%m detected an error!") ;
|
|
test_fail("PCI Master must didn't transfer 2 words in a burst, latency timer was set to a value of 2 and timeout occured") ;
|
|
ok = 0 ;
|
|
end
|
end
|
end
|
join
|
join
|
|
|
// check data provided by target
|
// check data provided by target
|
if ( ok )
|
if ( ok )
|
| Line 7809... |
Line 7945... |
test_fail("burst read interrupted by Latency Timeout didn't return expected data") ;
|
test_fail("burst read interrupted by Latency Timeout didn't return expected data") ;
|
ok = 0 ;
|
ok = 0 ;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
if ( ok )
|
if ( ok )
|
test_ok ;
|
test_ok ;
|
|
|
test_name = "DISABLE_IMAGE" ;
|
test_name = "DISABLE_IMAGE" ;
|
config_write( am_offset, 32'h7FFF_FFFF, 4'hF, ok ) ;
|
config_write( am_offset, 32'h7FFF_FFFF, 4'hF, ok ) ;
|
| Line 9224... |
Line 9361... |
input check_transfers ;
|
input check_transfers ;
|
input check_cycles ;
|
input check_cycles ;
|
input doing_fast_back_to_back ;
|
input doing_fast_back_to_back ;
|
output ok ;
|
output ok ;
|
reg in_use ;
|
reg in_use ;
|
integer deadlock_counter ;
|
|
integer transfer_counter ;
|
integer transfer_counter ;
|
integer cycle_counter ;
|
integer cycle_counter ;
|
integer deadlock_max_val ;
|
integer deadlock_max_val ;
|
begin:main
|
begin:main
|
|
|
| Line 9237... |
Line 9373... |
$display("pci_transaction_progress_monitor task re-entered! Time %t ", $time) ;
|
$display("pci_transaction_progress_monitor task re-entered! Time %t ", $time) ;
|
ok = 0 ;
|
ok = 0 ;
|
disable main ;
|
disable main ;
|
end
|
end
|
|
|
// approximate number of cycles on WB bus for maximum transaction length
|
|
deadlock_max_val = wb_init_waits + 100 +
|
|
`WBW_DEPTH *
|
|
(wb_subseq_waits + 1 +
|
|
`ifdef REGISTER_WBS_OUTPUTS
|
|
1) ;
|
|
`else
|
|
0) ;
|
|
`endif
|
|
|
|
// time used for maximum transaction length on WB
|
// number of ns to wait before timeout occurs
|
deadlock_max_val = deadlock_max_val * ( `WB_PERIOD ) ;
|
deadlock_max_val = `PCIW_DEPTH * 10 ;
|
|
deadlock_max_val = deadlock_max_val + `PCIR_DEPTH * 30 ;
|
|
|
// maximum pci clock cycles
|
// time used for maximum transaction length on PCI
|
`ifdef PCI33
|
`ifdef PCI33
|
deadlock_max_val = deadlock_max_val / 30 + 100 ;
|
deadlock_max_val = deadlock_max_val * ( 30 ) ;
|
`else
|
`else
|
deadlock_max_val = deadlock_max_val / 15 + 100 ;
|
deadlock_max_val = deadlock_max_val * ( 15 ) ;
|
`endif
|
`endif
|
|
|
|
deadlock_max_val = deadlock_max_val + (`WBW_DEPTH * 10 * `WB_PERIOD) ;
|
|
deadlock_max_val = deadlock_max_val + (`WBR_DEPTH * 30 * `WB_PERIOD) ;
|
|
|
in_use = 1 ;
|
in_use = 1 ;
|
ok = 1 ;
|
ok = 1 ;
|
|
|
fork
|
monitor32.get_pci_op.timeout_val = deadlock_max_val ;
|
begin:wait_start
|
|
|
|
deadlock_counter = 0 ;
|
|
|
|
@(posedge pci_clock) ;
|
begin:monitor_blk
|
|
reg [31:0 ] returned_adr ;
|
|
reg [ 3:0 ] returned_cmd ;
|
|
reg ret_gnt_deasserted ;
|
|
|
if ( doing_fast_back_to_back !== 1 )
|
monitor32.get_pci_op(returned_adr, returned_cmd) ;
|
begin
|
|
while ( (FRAME !== 1) && (deadlock_counter < deadlock_max_val) )
|
|
begin
|
|
if ( (IRDY == 0) && ((TRDY == 0) || (STOP == 0)) )
|
|
deadlock_counter = 0 ;
|
|
else
|
|
deadlock_counter = deadlock_counter + 1 ;
|
|
@(posedge pci_clock) ;
|
|
end
|
|
if ( FRAME !== 1 )
|
|
begin
|
|
$display("pci_transaction_progress_monitor task waited for 1000 cycles for previous transaction to complete! Time %t ", $time) ;
|
|
in_use = 0 ;
|
|
ok = 0 ;
|
|
disable main ;
|
|
end
|
|
end
|
|
|
|
deadlock_counter = 0 ;
|
|
while ( (FRAME !== 0) && (deadlock_counter < deadlock_max_val) )
|
|
begin
|
|
deadlock_counter = deadlock_counter + 1 ;
|
|
@(posedge pci_clock) ;
|
|
end
|
|
|
|
if ( FRAME !== 0 )
|
|
begin
|
|
$display("pci_transaction_progress_monitor task waited for 1000 cycles for transaction to start! Time %t ", $time) ;
|
|
in_use = 0 ;
|
|
ok = 0 ;
|
|
disable main ;
|
|
end
|
|
end //wait_start
|
|
|
|
begin:addr_bc_monitor
|
|
|
|
@(posedge pci_clock) ;
|
|
|
|
if ( doing_fast_back_to_back !== 1 )
|
|
begin
|
|
while ( FRAME !== 1 )
|
|
@(posedge pci_clock) ;
|
|
end
|
|
|
|
while( FRAME !== 0 )
|
|
@(posedge pci_clock) ;
|
|
|
|
// Address during Interrupt Acknowledge cycle has don't care value - don't check it
|
// Address during Interrupt Acknowledge cycle has don't care value - don't check it
|
if ( bus_command !== `BC_IACK )
|
if ( bus_command !== `BC_IACK )
|
begin
|
begin
|
if ( AD !== address )
|
if ( returned_adr !== address )
|
begin
|
begin
|
$display("pci_transaction_progress_monitor detected unexpected address on PCI! Time %t ", $time) ;
|
$display("pci_transaction_progress_monitor detected unexpected address on PCI! Time %t ", $time) ;
|
$display("Expected address = %h, detected address = %h ", address, AD) ;
|
$display("Expected address = %h, detected address = %h ", address, returned_adr) ;
|
ok = 0 ;
|
ok = 0 ;
|
end
|
end
|
end
|
end
|
|
|
if ( CBE !== bus_command )
|
if ( returned_cmd !== bus_command )
|
begin
|
begin
|
$display("pci_transaction_progress_monitor detected unexpected bus command on PCI! Time %t ", $time) ;
|
$display("pci_transaction_progress_monitor detected unexpected bus command on PCI! Time %t ", $time) ;
|
$display("Expected bus command = %b, detected bus command = %b", bus_command, CBE) ;
|
$display("Expected bus command = %b, detected bus command = %b", bus_command, returned_cmd) ;
|
ok = 0 ;
|
ok = 0 ;
|
end
|
end
|
end //addr_bc_monitor
|
|
|
|
begin:transfer_checker
|
|
transfer_counter = 0 ;
|
|
|
|
@(posedge pci_clock) ;
|
fork
|
|
|
if ( doing_fast_back_to_back !== 1 )
|
|
begin
|
|
while ( FRAME !== 1 )
|
|
@(posedge pci_clock) ;
|
|
end
|
|
|
|
while( FRAME !== 0 )
|
|
@(posedge pci_clock) ;
|
|
|
|
while( FRAME === 0 )
|
|
begin
|
|
if ( (IRDY === 0) && (TRDY === 0) && (DEVSEL === 0) )
|
|
transfer_counter = transfer_counter + 1 ;
|
|
@(posedge pci_clock) ;
|
|
end
|
|
|
|
while( (IRDY === 0) && (TRDY === 1) && (STOP === 1) )
|
|
begin
|
begin
|
@(posedge pci_clock) ;
|
|
end
|
|
|
|
if ( (TRDY === 0) && (DEVSEL === 0) )
|
|
transfer_counter = transfer_counter + 1 ;
|
|
|
|
if ( check_transfers === 1 )
|
if ( check_transfers === 1 )
|
begin
|
begin
|
|
monitor32.get_pci_op_num_of_transfers(transfer_counter, ret_gnt_deasserted) ;
|
if ( transfer_counter !== num_of_transfers )
|
if ( transfer_counter !== num_of_transfers )
|
begin
|
begin
|
$display("pci_transaction_progress_monitor detected unexpected transaction! Time %t ", $time) ;
|
$display("pci_transaction_progress_monitor detected unexpected transaction! Time %t ", $time) ;
|
$display("Expected transfers in transaction = %d, actual transfers = %d ", num_of_transfers, transfer_counter) ;
|
$display("Expected transfers in transaction = %d, actual transfers = %d ", num_of_transfers, transfer_counter) ;
|
ok = 0 ;
|
ok = 0 ;
|
end
|
end
|
end
|
end
|
end //transfer_checker
|
|
begin:cycle_checker
|
|
if ( check_cycles )
|
|
begin
|
|
cycle_counter = 0 ;
|
|
@(posedge pci_clock) ;
|
|
|
|
if ( doing_fast_back_to_back !== 1)
|
|
begin
|
|
while ( FRAME !== 1 )
|
|
@(posedge pci_clock) ;
|
|
end
|
end
|
|
|
while( FRAME !== 0 )
|
|
@(posedge pci_clock) ;
|
|
|
|
while ( (FRAME !== 1) && (cycle_counter < num_of_cycles) )
|
|
begin
|
begin
|
cycle_counter = cycle_counter + 1 ;
|
if ( check_cycles === 1'b1)
|
@(posedge pci_clock) ;
|
|
end
|
|
|
|
if ( FRAME !== 1 )
|
|
begin
|
begin
|
while ((FRAME === 0) && (MAS0_GNT === 0))
|
monitor32.get_pci_op_num_of_cycles(cycle_counter) ;
|
@(posedge pci_clock) ;
|
if (cycle_counter > num_of_cycles)
|
|
|
if ( FRAME !== 1 )
|
|
begin
|
|
while( (IRDY === 1) || ((TRDY === 1) && (STOP === 1)) )
|
|
@(posedge pci_clock) ;
|
|
|
|
@(posedge pci_clock) ;
|
|
|
|
if ( FRAME !== 1 )
|
|
begin
|
begin
|
$display("pci_transaction_progress_monitor detected invalid transaction length! Time %t ", $time) ;
|
$display("pci_transaction_progress_monitor detected invalid transaction length! Time %t ", $time) ;
|
$display("Possibility of wrong operation in latency timer logic exists!") ;
|
$display("Possibility of wrong operation in latency timer logic exists!") ;
|
ok = 0 ;
|
ok = 0 ;
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
|
end // cycle_checker
|
|
join
|
join
|
|
|
|
end //monitor_blk
|
|
|
in_use = 0 ;
|
in_use = 0 ;
|
|
|
end
|
end
|
endtask //pci_transaction_progress_monitor
|
endtask //pci_transaction_progress_monitor
|
|
|
reg CYC_O_previous ;
|
reg CYC_O_previous ;
|
always@(posedge wb_clock or posedge reset)
|
always@(posedge wb_clock or posedge reset)
|
| Line 9438... |
Line 9468... |
input write ;
|
input write ;
|
input [31:0] num_of_transfers ;
|
input [31:0] num_of_transfers ;
|
input check_transfers ;
|
input check_transfers ;
|
output ok ;
|
output ok ;
|
reg in_use ;
|
reg in_use ;
|
integer deadlock_counter ;
|
|
integer transfer_counter ;
|
integer transfer_counter ;
|
integer deadlock_max_val ;
|
integer deadlock_max_val ;
|
reg [2:0] slave_termination ;
|
reg [2:0] slave_termination ;
|
reg cab_asserted ;
|
reg cab_asserted ;
|
begin:main
|
begin:main
|
| Line 9451... |
Line 9480... |
$display("wb_transaction_progress_monitor task re-entered! Time %t ", $time) ;
|
$display("wb_transaction_progress_monitor task re-entered! Time %t ", $time) ;
|
ok = 0 ;
|
ok = 0 ;
|
disable main ;
|
disable main ;
|
end
|
end
|
|
|
// number of cycles on WB bus for maximum transaction length
|
// number of ns to wait before timeout occurs
|
deadlock_max_val = pci_init_waits + 100 +
|
deadlock_max_val = `PCIW_DEPTH * 10 ;
|
`PCIW_DEPTH *
|
deadlock_max_val = deadlock_max_val + `PCIR_DEPTH * 30 ;
|
(pci_subseq_waits + 1) ;
|
|
|
|
// time used for maximum transaction length on PCI
|
// time used for maximum transaction length on PCI
|
`ifdef PCI33
|
`ifdef PCI33
|
deadlock_max_val = deadlock_max_val * ( 30 ) + 100 ;
|
deadlock_max_val = deadlock_max_val * ( 30 ) ;
|
`else
|
`else
|
deadlock_max_val = deadlock_max_val * ( 15 ) + 100 ;
|
deadlock_max_val = deadlock_max_val * ( 15 ) ;
|
`endif
|
`endif
|
|
|
// maximum wb clock cycles
|
deadlock_max_val = deadlock_max_val + (`WBW_DEPTH * 10 * `WB_PERIOD) ;
|
deadlock_max_val = deadlock_max_val / (`WB_PERIOD) ;
|
deadlock_max_val = deadlock_max_val + (`WBR_DEPTH * 30 * `WB_PERIOD) ;
|
|
|
in_use = 1 ;
|
in_use = 1 ;
|
ok = 1 ;
|
ok = 1 ;
|
cab_asserted = 0 ;
|
cab_asserted = 0 ;
|
|
|
fork
|
fork
|
begin:wait_start
|
begin:wait_start
|
deadlock_counter = 0 ;
|
#(deadlock_max_val) ;
|
@(posedge wb_clock) ;
|
$display("%m timeout! Time %t ", $time) ;
|
while ( (CYC_O !== 0 && CYC_O_previous !== 0) && (deadlock_counter < deadlock_max_val) )
|
|
begin
|
|
if ((!STB_O) || (!ACK_I && !RTY_I && !ERR_I))
|
|
deadlock_counter = deadlock_counter + 1 ;
|
|
else
|
|
deadlock_counter = 0;
|
|
@(posedge wb_clock) ;
|
|
end
|
|
if ( CYC_O !== 0 && CYC_O_previous !== 0)
|
|
begin
|
|
$display("wb_transaction_progress_monitor task waited for 1000 cycles for previous transaction to complete! Time %t ", $time) ;
|
|
in_use = 0 ;
|
|
ok = 0 ;
|
|
disable main ;
|
|
end
|
|
|
|
deadlock_counter = 0 ;
|
|
while ( (CYC_O !== 1) && (deadlock_counter < deadlock_max_val) )
|
|
begin
|
|
deadlock_counter = deadlock_counter + 1 ;
|
|
@(posedge wb_clock) ;
|
|
end
|
|
|
|
if ( CYC_O !== 1 )
|
|
begin
|
|
$display("wb_transaction_progress_monitor task waited for 1000 cycles for transaction to start! Time %t ", $time) ;
|
|
in_use = 0 ;
|
in_use = 0 ;
|
ok = 0 ;
|
ok = 0 ;
|
disable main ;
|
disable main ;
|
end
|
|
end //wait_start
|
end //wait_start
|
begin:addr_monitor
|
begin:addr_monitor
|
@(posedge wb_clock) ;
|
@(posedge wb_clock) ;
|
while ( CYC_O !== 0 && CYC_O_previous !== 0)
|
while ( CYC_O !== 0 && CYC_O_previous !== 0)
|
@(posedge wb_clock) ;
|
@(posedge wb_clock) ;
|
| Line 9531... |
Line 9532... |
begin
|
begin
|
$display("wb_transaction_progress_monitor detected unexpected address on WB bus! Time %t ", $time) ;
|
$display("wb_transaction_progress_monitor detected unexpected address on WB bus! Time %t ", $time) ;
|
$display("Expected address = %h, detected address = %h ", address, ADR_O) ;
|
$display("Expected address = %h, detected address = %h ", address, ADR_O) ;
|
ok = 0 ;
|
ok = 0 ;
|
end
|
end
|
|
disable wait_start ;
|
end
|
end
|
begin:transfer_checker
|
begin:transfer_checker
|
transfer_counter = 0 ;
|
transfer_counter = 0 ;
|
@(posedge wb_clock) ;
|
@(posedge wb_clock) ;
|
while ( CYC_O !== 0 && CYC_O_previous !== 0)
|
while ( CYC_O !== 0 && CYC_O_previous !== 0)
|
| Line 9612... |
Line 9614... |
input write ;
|
input write ;
|
input [31:0] num_of_transfers ;
|
input [31:0] num_of_transfers ;
|
input check_transfers ;
|
input check_transfers ;
|
output ok ;
|
output ok ;
|
reg in_use ;
|
reg in_use ;
|
integer deadlock_counter ;
|
|
integer transfer_counter ;
|
integer transfer_counter ;
|
integer deadlock_max_val ;
|
integer deadlock_max_val ;
|
begin:main
|
begin:main
|
if ( in_use === 1 )
|
if ( in_use === 1 )
|
begin
|
begin
|
$display("wb_transaction_progress_monitor task re-entered! Time %t ", $time) ;
|
$display("wb_transaction_progress_monitor task re-entered! Time %t ", $time) ;
|
ok = 0 ;
|
ok = 0 ;
|
disable main ;
|
disable main ;
|
end
|
end
|
|
|
// number of cycles on WB bus for maximum transaction length
|
// number of ns to wait before timeout occurs
|
deadlock_max_val = pci_init_waits + 100 +
|
deadlock_max_val = `PCIW_DEPTH * 10 ;
|
`PCIW_DEPTH *
|
deadlock_max_val = deadlock_max_val + `PCIR_DEPTH * 30 ;
|
(pci_subseq_waits + 1) ;
|
|
|
|
// time used for maximum transaction length on PCI
|
// time used for maximum transaction length on PCI
|
`ifdef PCI33
|
`ifdef PCI33
|
deadlock_max_val = deadlock_max_val * ( 30 ) + 100 ;
|
deadlock_max_val = deadlock_max_val * ( 30 ) ;
|
`else
|
`else
|
deadlock_max_val = deadlock_max_val * ( 15 ) + 100 ;
|
deadlock_max_val = deadlock_max_val * ( 15 ) ;
|
`endif
|
`endif
|
|
|
// maximum wb clock cycles
|
deadlock_max_val = deadlock_max_val + (`WBW_DEPTH * 10 * `WB_PERIOD) ;
|
deadlock_max_val = deadlock_max_val / (`WB_PERIOD) ;
|
deadlock_max_val = deadlock_max_val + (`WBR_DEPTH * 30 * `WB_PERIOD) ;
|
|
|
in_use = 1 ;
|
in_use = 1 ;
|
ok = 1 ;
|
ok = 1 ;
|
|
|
fork
|
fork
|
begin:wait_start
|
begin:wait_start
|
deadlock_counter = 0 ;
|
#(deadlock_max_val) ;
|
@(posedge wb_clock) ;
|
$display("%m timeout! Time %t ", $time) ;
|
while ( (CYC_O !== 0) && (deadlock_counter < deadlock_max_val) )
|
|
begin
|
|
if ((!STB_O) || (!ACK_I && !RTY_I && !ERR_I))
|
|
deadlock_counter = deadlock_counter + 1 ;
|
|
else
|
|
deadlock_counter = 0;
|
|
@(posedge wb_clock) ;
|
|
end
|
|
if ( CYC_O !== 0 )
|
|
begin
|
|
$display("wb_transaction_progress_monitor task waited for 1000 cycles for previous transaction to complete! Time %t ", $time) ;
|
|
in_use = 0 ;
|
|
ok = 0 ;
|
|
disable main ;
|
|
end
|
|
|
|
deadlock_counter = 0 ;
|
|
while ( (CYC_O !== 1) && (deadlock_counter < deadlock_max_val) )
|
|
begin
|
|
deadlock_counter = deadlock_counter + 1 ;
|
|
@(posedge wb_clock) ;
|
|
end
|
|
|
|
if ( CYC_O !== 1 )
|
|
begin
|
|
$display("wb_transaction_progress_monitor task waited for 1000 cycles for transaction to start! Time %t ", $time) ;
|
|
in_use = 0 ;
|
in_use = 0 ;
|
ok = 0 ;
|
ok = 0 ;
|
disable main ;
|
disable main ;
|
end
|
|
end //wait_start
|
end //wait_start
|
begin:addr_monitor
|
begin:addr_monitor
|
@(posedge wb_clock) ;
|
@(posedge wb_clock) ;
|
while ( CYC_O !== 0 )
|
while ( CYC_O !== 0 )
|
@(posedge wb_clock) ;
|
@(posedge wb_clock) ;
|
| Line 9702... |
Line 9675... |
begin
|
begin
|
$display("wb_transaction_progress_monitor detected unexpected address on WB bus! Time %t ", $time) ;
|
$display("wb_transaction_progress_monitor detected unexpected address on WB bus! Time %t ", $time) ;
|
$display("Expected address = %h, detected address = %h ", address, ADR_O) ;
|
$display("Expected address = %h, detected address = %h ", address, ADR_O) ;
|
ok = 0 ;
|
ok = 0 ;
|
end
|
end
|
|
disable wait_start ;
|
end
|
end
|
begin:transfer_checker
|
begin:transfer_checker
|
transfer_counter = 0 ;
|
transfer_counter = 0 ;
|
@(posedge wb_clock) ;
|
@(posedge wb_clock) ;
|
while ( CYC_O !== 0 )
|
while ( CYC_O !== 0 )
|
| Line 10317... |
Line 10291... |
reg [31:0] pci_address ;
|
reg [31:0] pci_address ;
|
reg in_use ;
|
reg in_use ;
|
reg ok ;
|
reg ok ;
|
|
|
reg [31:0] temp_var ;
|
reg [31:0] temp_var ;
|
|
integer i ;
|
begin:main
|
begin:main
|
|
|
|
if (read0_write1 === 1'b0)
|
|
data = 32'hxxxx_xxxx ;
|
|
|
if ( in_use === 1 )
|
if ( in_use === 1 )
|
begin
|
begin
|
$display("generate_configuration_cycle task re-entered! Time %t ", $time) ;
|
$display("generate_configuration_cycle task re-entered! Time %t ", $time) ;
|
data = 32'hxxxx_xxxx ;
|
data = 32'hxxxx_xxxx ;
|
disable main ;
|
disable main ;
|
| Line 10338... |
Line 10316... |
pci_address[10:0] = { func_num, reg_num, type } ;
|
pci_address[10:0] = { func_num, reg_num, type } ;
|
if (device_num <= 20)
|
if (device_num <= 20)
|
pci_address[11 + device_num] = 1'b1 ;
|
pci_address[11 + device_num] = 1'b1 ;
|
end
|
end
|
|
|
// setup flags
|
// setup flags
|
flags = 0 ;
|
flags = 0 ;
|
flags`INIT_WAITS = wb_init_waits ;
|
flags`INIT_WAITS = wb_init_waits ;
|
flags`SUBSEQ_WAITS = wb_subseq_waits ;
|
flags`SUBSEQ_WAITS = wb_subseq_waits ;
|
|
|
|
temp_var = { `WB_CONFIGURATION_BASE, 12'h000 } ;
|
|
temp_var[(31 - `WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
|
|
|
|
write_data`WRITE_ADDRESS = temp_var + { 4'h1, `CNF_ADDR_ADDR, 2'b00 } ;
|
|
write_data`WRITE_DATA = { 8'h00, bus_num, device_num, func_num, reg_num, type } ;
|
|
|
|
`ifdef PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS
|
|
|
|
write_data`WRITE_SEL = 4'b0001 ;
|
|
repeat(4)
|
|
begin
|
|
wishbone_master.wb_single_write(write_data, flags, write_status) ;
|
|
|
|
// check if write succeeded
|
|
if (write_status`CYC_ACTUAL_TRANSFER !== 1)
|
|
begin
|
|
$display("Configuration cycle generation failed! Couldn't write to configuration address register! Time %t ", $time) ;
|
|
in_use = 0 ;
|
|
disable main ;
|
|
end
|
|
|
|
write_data`WRITE_ADDRESS = write_data`WRITE_ADDRESS + 'h1 ;
|
|
write_data`WRITE_SEL = write_data`WRITE_SEL << 1 ;
|
|
end
|
|
|
temp_var = { `WB_CONFIGURATION_BASE, 12'h000 } ;
|
`else
|
temp_var[(31 - `WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
|
|
|
|
write_data`WRITE_ADDRESS = temp_var + { 4'h1, `CNF_ADDR_ADDR, 2'b00 } ;
|
|
write_data`WRITE_DATA = { 8'h00, bus_num, device_num, func_num, reg_num, type } ;
|
|
write_data`WRITE_SEL = 4'hF ;
|
write_data`WRITE_SEL = 4'hF ;
|
write_data`WRITE_TAG_STIM = 0 ;
|
|
|
|
wishbone_master.wb_single_write(write_data, flags, write_status) ;
|
wishbone_master.wb_single_write(write_data, flags, write_status) ;
|
|
|
// check if write succeeded
|
// check if write succeeded
|
if (write_status`CYC_ACTUAL_TRANSFER !== 1)
|
if (write_status`CYC_ACTUAL_TRANSFER !== 1)
|
begin
|
begin
|
$display("Configuration cycle generation failed! Couldn't write to configuration address register! Time %t ", $time) ;
|
$display("Configuration cycle generation failed! Couldn't write to configuration address register! Time %t ", $time) ;
|
data = 32'hxxxx_xxxx ;
|
|
in_use = 0 ;
|
in_use = 0 ;
|
disable main ;
|
disable main ;
|
end
|
end
|
|
|
|
`endif
|
|
|
// setup flags for wb master to handle retries and read and write data
|
// setup flags for wb master to handle retries and read and write data
|
flags`WB_TRANSFER_AUTO_RTY = 1 ;
|
flags`WB_TRANSFER_AUTO_RTY = 1 ;
|
|
|
read_data`READ_ADDRESS = temp_var + {4'b0001, `CNF_DATA_ADDR, 2'b00} ;
|
read_data`READ_ADDRESS = temp_var + {4'b0001, `CNF_DATA_ADDR, 2'b00} ;
|
write_data`WRITE_ADDRESS = read_data`READ_ADDRESS ;
|
write_data`WRITE_ADDRESS = read_data`READ_ADDRESS ;
|
read_data`READ_SEL = byte_enables ;
|
read_data`READ_SEL = byte_enables ;
|
write_data`WRITE_SEL = byte_enables ;
|
write_data`WRITE_SEL = byte_enables ;
|
read_data`READ_TAG_STIM = 0 ;
|
|
write_data`WRITE_TAG_STIM = 0 ;
|
|
write_data`WRITE_DATA = data ;
|
write_data`WRITE_DATA = data ;
|
|
|
ok = 0 ;
|
ok = 0 ;
|
|
|
|
temp_var = 32'hxxxx_xxxx ;
|
|
|
|
`ifdef PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS
|
|
|
|
for (i = 0 ; i < 4 ; i = i + 1)
|
|
begin
|
|
|
|
if (byte_enables[i] === 1'b1)
|
|
begin
|
|
read_data`READ_SEL = 4'h1 << i ;
|
|
write_data`WRITE_SEL = read_data`READ_SEL ;
|
|
|
|
`else
|
|
|
|
begin
|
|
begin
|
|
|
|
`endif
|
|
|
fork
|
fork
|
begin
|
begin
|
if (read0_write1 === 0)
|
if (read0_write1 === 0)
|
wishbone_master.wb_single_read(read_data, flags, read_status) ;
|
wishbone_master.wb_single_read(read_data, flags, read_status) ;
|
else
|
else if (read0_write1 === 1)
|
if (read0_write1 === 1)
|
|
wishbone_master.wb_single_write(write_data, flags, write_status) ;
|
wishbone_master.wb_single_write(write_data, flags, write_status) ;
|
|
|
|
|
|
// check if transfer succeeded
|
|
if ((read0_write1 ? write_status`CYC_ACTUAL_TRANSFER : read_status`CYC_ACTUAL_TRANSFER) !== 1)
|
|
begin
|
|
$display("Configuration cycle generation failed! Configuration cycle not processed correctly by the bridge! Time %t ", $time) ;
|
|
data = 32'hxxxx_xxxx ;
|
|
in_use = 0 ;
|
|
disable main ;
|
|
end
|
|
|
end
|
end
|
begin
|
begin
|
pci_transaction_progress_monitor
|
pci_transaction_progress_monitor
|
(
|
(
|
pci_address, // expected address on PCI bus
|
pci_address, // expected address on PCI bus
|
| Line 10395... |
Line 10421... |
1'b0, // monitor checking/not checking number of transfers
|
1'b0, // monitor checking/not checking number of transfers
|
1'b0, // monitor checking/not checking number of cycles
|
1'b0, // monitor checking/not checking number of cycles
|
0, // tell to monitor if it has to expect a fast back to back transaction
|
0, // tell to monitor if it has to expect a fast back to back transaction
|
ok // status - 1 success, 0 failure
|
ok // status - 1 success, 0 failure
|
) ;
|
) ;
|
end
|
|
join
|
|
|
|
// check if transfer succeeded
|
if (!ok)
|
if ((read0_write1 ? write_status`CYC_ACTUAL_TRANSFER : read_status`CYC_ACTUAL_TRANSFER) !== 1)
|
|
begin
|
begin
|
$display("Configuration cycle generation failed! Configuration cycle not processed correctly by the bridge! Time %t ", $time) ;
|
|
data = 32'hxxxx_xxxx ;
|
data = 32'hxxxx_xxxx ;
|
in_use = 0 ;
|
in_use = 0 ;
|
disable main ;
|
disable main ;
|
end
|
end
|
|
end
|
|
join
|
|
|
if (!ok)
|
`ifdef PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS
|
|
|
|
temp_var = read_status`READ_DATA ;
|
|
|
|
if (read0_write1 === 0)
|
begin
|
begin
|
data = 32'hxxxx_xxxx ;
|
case(read_data`READ_SEL)
|
in_use = 0 ;
|
4'b0001:data[ 7:0 ] = temp_var[ 7:0 ] ;
|
disable main ;
|
4'b0010:data[15:8 ] = temp_var[15:8 ] ;
|
|
4'b0100:data[23:16] = temp_var[23:16] ;
|
|
4'b1000:data[31:24] = temp_var[31:24] ;
|
|
endcase
|
end
|
end
|
|
|
|
`else
|
|
|
if (read0_write1 === 0)
|
if (read0_write1 === 0)
|
data = read_status`READ_DATA ;
|
data = read_status`READ_DATA ;
|
|
|
|
`endif
|
|
|
|
end
|
|
read_data`READ_ADDRESS = read_data`READ_ADDRESS + 1'b1 ;
|
|
write_data`WRITE_ADDRESS = write_data`WRITE_ADDRESS + 1'b1 ;
|
|
end
|
|
|
in_use = 0 ;
|
in_use = 0 ;
|
end
|
end
|
endtask // generate_configuration_cycle
|
endtask // generate_configuration_cycle
|
|
|
task test_configuration_cycle_target_abort ;
|
task test_configuration_cycle_target_abort ;
|
| Line 10464... |
Line 10504... |
write_data`WRITE_ADDRESS = temp_var + { 4'h1, `CNF_ADDR_ADDR, 2'b00 } ;
|
write_data`WRITE_ADDRESS = temp_var + { 4'h1, `CNF_ADDR_ADDR, 2'b00 } ;
|
temp_var = 0 ;
|
temp_var = 0 ;
|
temp_var[15:11] = `TAR1_IDSEL_INDEX - 11 ; // device number field
|
temp_var[15:11] = `TAR1_IDSEL_INDEX - 11 ; // device number field
|
write_data`WRITE_DATA = temp_var ;
|
write_data`WRITE_DATA = temp_var ;
|
write_data`WRITE_SEL = 4'hF ;
|
write_data`WRITE_SEL = 4'hF ;
|
write_data`WRITE_TAG_STIM = 0 ;
|
|
|
|
wishbone_master.wb_single_write(write_data, flags, write_status) ;
|
wishbone_master.wb_single_write(write_data, flags, write_status) ;
|
|
|
// check if write succeeded
|
// check if write succeeded
|
if (write_status`CYC_ACTUAL_TRANSFER !== 1)
|
if (write_status`CYC_ACTUAL_TRANSFER !== 1)
|
| Line 10487... |
Line 10526... |
|
|
read_data`READ_ADDRESS = temp_var + {4'b0001, `CNF_DATA_ADDR, 2'b00} ;
|
read_data`READ_ADDRESS = temp_var + {4'b0001, `CNF_DATA_ADDR, 2'b00} ;
|
write_data`WRITE_ADDRESS = read_data`READ_ADDRESS ;
|
write_data`WRITE_ADDRESS = read_data`READ_ADDRESS ;
|
read_data`READ_SEL = 4'hF ;
|
read_data`READ_SEL = 4'hF ;
|
write_data`WRITE_SEL = 4'hF ;
|
write_data`WRITE_SEL = 4'hF ;
|
read_data`READ_TAG_STIM = 0 ;
|
|
write_data`WRITE_TAG_STIM = 0 ;
|
|
write_data`WRITE_DATA = 32'hAAAA_AAAA ;
|
write_data`WRITE_DATA = 32'hAAAA_AAAA ;
|
|
|
ok_pci = 0 ;
|
ok_pci = 0 ;
|
ok_wb = 1 ;
|
ok_wb = 1 ;
|
|
|
| Line 10667... |
Line 10704... |
temp_var[(31 - `WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
|
temp_var[(31 - `WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
|
|
|
write_data`WRITE_ADDRESS = temp_var + { 4'h1, `CNF_ADDR_ADDR, 2'b00 } ;
|
write_data`WRITE_ADDRESS = temp_var + { 4'h1, `CNF_ADDR_ADDR, 2'b00 } ;
|
write_data`WRITE_DATA = pci_address ;
|
write_data`WRITE_DATA = pci_address ;
|
write_data`WRITE_SEL = 4'hF ;
|
write_data`WRITE_SEL = 4'hF ;
|
write_data`WRITE_TAG_STIM = 0 ;
|
|
|
|
wishbone_master.wb_single_write(write_data, flags, write_status) ;
|
wishbone_master.wb_single_write(write_data, flags, write_status) ;
|
|
|
// check if write succeeded
|
// check if write succeeded
|
if (write_status`CYC_ACTUAL_TRANSFER !== 1)
|
if (write_status`CYC_ACTUAL_TRANSFER !== 1)
|
| Line 10690... |
Line 10726... |
|
|
read_data`READ_ADDRESS = temp_var + {4'b0001, `CNF_DATA_ADDR, 2'b00} ;
|
read_data`READ_ADDRESS = temp_var + {4'b0001, `CNF_DATA_ADDR, 2'b00} ;
|
write_data`WRITE_ADDRESS = read_data`READ_ADDRESS ;
|
write_data`WRITE_ADDRESS = read_data`READ_ADDRESS ;
|
read_data`READ_SEL = 4'hF ;
|
read_data`READ_SEL = 4'hF ;
|
write_data`WRITE_SEL = 4'hF ;
|
write_data`WRITE_SEL = 4'hF ;
|
read_data`READ_TAG_STIM = 0 ;
|
|
write_data`WRITE_TAG_STIM = 0 ;
|
|
write_data`WRITE_DATA = 32'hAAAA_AAAA ;
|
write_data`WRITE_DATA = 32'hAAAA_AAAA ;
|
|
|
ok_pci = 0 ;
|
ok_pci = 0 ;
|
ok_wb = 1 ;
|
ok_wb = 1 ;
|
|
|
| Line 10830... |
Line 10864... |
temp_var[(31 - `WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
|
temp_var[(31 - `WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
|
|
|
write_data`WRITE_ADDRESS = temp_var + { 4'h1, `CNF_ADDR_ADDR, 2'b00 } ;
|
write_data`WRITE_ADDRESS = temp_var + { 4'h1, `CNF_ADDR_ADDR, 2'b00 } ;
|
write_data`WRITE_DATA = pci_address ;
|
write_data`WRITE_DATA = pci_address ;
|
write_data`WRITE_SEL = 4'hF ;
|
write_data`WRITE_SEL = 4'hF ;
|
write_data`WRITE_TAG_STIM = 0 ;
|
|
|
|
wishbone_master.wb_single_write(write_data, flags, write_status) ;
|
wishbone_master.wb_single_write(write_data, flags, write_status) ;
|
|
|
// check if write succeeded
|
// check if write succeeded
|
if (write_status`CYC_ACTUAL_TRANSFER !== 1)
|
if (write_status`CYC_ACTUAL_TRANSFER !== 1)
|
| Line 10853... |
Line 10886... |
|
|
read_data`READ_ADDRESS = temp_var + {4'b0001, `CNF_DATA_ADDR, 2'b00} ;
|
read_data`READ_ADDRESS = temp_var + {4'b0001, `CNF_DATA_ADDR, 2'b00} ;
|
write_data`WRITE_ADDRESS = read_data`READ_ADDRESS ;
|
write_data`WRITE_ADDRESS = read_data`READ_ADDRESS ;
|
read_data`READ_SEL = 4'hF ;
|
read_data`READ_SEL = 4'hF ;
|
write_data`WRITE_SEL = 4'hF ;
|
write_data`WRITE_SEL = 4'hF ;
|
read_data`READ_TAG_STIM = 0 ;
|
|
write_data`WRITE_TAG_STIM = 0 ;
|
|
write_data`WRITE_DATA = 32'hAAAA_AAAA ;
|
write_data`WRITE_DATA = 32'hAAAA_AAAA ;
|
|
|
ok_pci = 0 ;
|
ok_pci = 0 ;
|
ok_wb = 1 ;
|
ok_wb = 1 ;
|
|
|
| Line 10993... |
Line 11024... |
temp_var[(31 - `WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
|
temp_var[(31 - `WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
|
|
|
write_data`WRITE_ADDRESS = temp_var + { 4'h1, `CNF_ADDR_ADDR, 2'b00 } ;
|
write_data`WRITE_ADDRESS = temp_var + { 4'h1, `CNF_ADDR_ADDR, 2'b00 } ;
|
write_data`WRITE_DATA = pci_address ;
|
write_data`WRITE_DATA = pci_address ;
|
write_data`WRITE_SEL = 4'hF ;
|
write_data`WRITE_SEL = 4'hF ;
|
write_data`WRITE_TAG_STIM = 0 ;
|
|
|
|
wishbone_master.wb_single_write(write_data, flags, write_status) ;
|
wishbone_master.wb_single_write(write_data, flags, write_status) ;
|
|
|
// check if write succeeded
|
// check if write succeeded
|
if (write_status`CYC_ACTUAL_TRANSFER !== 1)
|
if (write_status`CYC_ACTUAL_TRANSFER !== 1)
|
| Line 11016... |
Line 11046... |
|
|
read_data`READ_ADDRESS = temp_var + {4'b0001, `CNF_DATA_ADDR, 2'b00} ;
|
read_data`READ_ADDRESS = temp_var + {4'b0001, `CNF_DATA_ADDR, 2'b00} ;
|
write_data`WRITE_ADDRESS = read_data`READ_ADDRESS ;
|
write_data`WRITE_ADDRESS = read_data`READ_ADDRESS ;
|
read_data`READ_SEL = 4'b0101 ;
|
read_data`READ_SEL = 4'b0101 ;
|
write_data`WRITE_SEL = 4'b1010 ;
|
write_data`WRITE_SEL = 4'b1010 ;
|
read_data`READ_TAG_STIM = 0 ;
|
|
write_data`WRITE_TAG_STIM = 0 ;
|
|
write_data`WRITE_DATA = 32'hAAAA_AAAA ;
|
write_data`WRITE_DATA = 32'hAAAA_AAAA ;
|
|
|
ok_pci = 0 ;
|
ok_pci = 0 ;
|
ok_wb = 1 ;
|
ok_wb = 1 ;
|
|
|
| Line 12488... |
Line 12516... |
write_flags`SUBSEQ_WAITS = wb_subseq_waits ;
|
write_flags`SUBSEQ_WAITS = wb_subseq_waits ;
|
write_flags`WB_TRANSFER_AUTO_RTY = 0 ;
|
write_flags`WB_TRANSFER_AUTO_RTY = 0 ;
|
|
|
write_data`WRITE_ADDRESS = { `WB_CONFIGURATION_BASE, offset } ;
|
write_data`WRITE_ADDRESS = { `WB_CONFIGURATION_BASE, offset } ;
|
write_data`WRITE_SEL = 4'h1 ;
|
write_data`WRITE_SEL = 4'h1 ;
|
write_data`WRITE_TAG_STIM = 0 ;
|
|
write_data`WRITE_DATA = data ;
|
write_data`WRITE_DATA = data ;
|
|
|
next_test_name[79:0] <= "Init_Tar_R";
|
next_test_name[79:0] <= "Init_Tar_R";
|
|
|
$display(" bridge target - Enabling master and target operation!");
|
$display(" bridge target - Enabling master and target operation!");
|
| Line 12508... |
Line 12535... |
offset = {4'h1, `P_BA0_ADDR, 2'b00} ; // PCI Base Address 0
|
offset = {4'h1, `P_BA0_ADDR, 2'b00} ; // PCI Base Address 0
|
data = Target_Base_Addr_R[0] ; // `TAR0_BASE_ADDR_0 = 32'h1000_0000
|
data = Target_Base_Addr_R[0] ; // `TAR0_BASE_ADDR_0 = 32'h1000_0000
|
|
|
write_data`WRITE_ADDRESS = temp_var + offset ;
|
write_data`WRITE_ADDRESS = temp_var + offset ;
|
write_data`WRITE_SEL = 4'hf ;
|
write_data`WRITE_SEL = 4'hf ;
|
write_data`WRITE_TAG_STIM = 0 ;
|
|
write_data`WRITE_DATA = data ;
|
write_data`WRITE_DATA = data ;
|
|
|
`ifdef NO_CNF_IMAGE
|
`ifdef NO_CNF_IMAGE
|
`ifdef PCI_IMAGE0 // set P_BA0
|
`ifdef PCI_IMAGE0 // set P_BA0
|
|
|
| Line 12589... |
Line 12615... |
temp_var = { `WB_CONFIGURATION_BASE, 12'h000 } ;
|
temp_var = { `WB_CONFIGURATION_BASE, 12'h000 } ;
|
temp_var[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
|
temp_var[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
|
|
|
write_data`WRITE_ADDRESS = temp_var + offset ;
|
write_data`WRITE_ADDRESS = temp_var + offset ;
|
write_data`WRITE_SEL = 4'h1 ;
|
write_data`WRITE_SEL = 4'h1 ;
|
write_data`WRITE_TAG_STIM = 0 ;
|
|
write_data`WRITE_DATA = data ;
|
write_data`WRITE_DATA = data ;
|
|
|
next_test_name[79:0] <= "Init_Tar_R";
|
next_test_name[79:0] <= "Init_Tar_R";
|
|
|
$display(" bridge target - Enabling master and target operation!");
|
$display(" bridge target - Enabling master and target operation!");
|
| Line 12606... |
Line 12631... |
offset = {4'h1, `P_BA0_ADDR, 2'b00} ; // PCI Base Address 0
|
offset = {4'h1, `P_BA0_ADDR, 2'b00} ; // PCI Base Address 0
|
data = Target_Base_Addr_R[0] ; // `TAR0_BASE_ADDR_0 = 32'h1000_0000
|
data = Target_Base_Addr_R[0] ; // `TAR0_BASE_ADDR_0 = 32'h1000_0000
|
|
|
write_data`WRITE_ADDRESS = temp_var + offset ;
|
write_data`WRITE_ADDRESS = temp_var + offset ;
|
write_data`WRITE_SEL = 4'hf ;
|
write_data`WRITE_SEL = 4'hf ;
|
write_data`WRITE_TAG_STIM = 0 ;
|
|
write_data`WRITE_DATA = data ;
|
write_data`WRITE_DATA = data ;
|
|
|
`ifdef NO_CNF_IMAGE
|
`ifdef NO_CNF_IMAGE
|
`ifdef PCI_IMAGE0 // set P_BA0
|
`ifdef PCI_IMAGE0 // set P_BA0
|
|
|
| Line 12633... |
Line 12657... |
offset = {4'h1, `P_BA1_ADDR, 2'b00} ; // PCI Base Address 1
|
offset = {4'h1, `P_BA1_ADDR, 2'b00} ; // PCI Base Address 1
|
data = Target_Base_Addr_R[1] ; // `TAR0_BASE_ADDR_1 = 32'h2000_0000
|
data = Target_Base_Addr_R[1] ; // `TAR0_BASE_ADDR_1 = 32'h2000_0000
|
|
|
write_data`WRITE_ADDRESS = temp_var + offset ;
|
write_data`WRITE_ADDRESS = temp_var + offset ;
|
write_data`WRITE_SEL = 4'hf ;
|
write_data`WRITE_SEL = 4'hf ;
|
write_data`WRITE_TAG_STIM = 0 ;
|
|
write_data`WRITE_DATA = data ;
|
write_data`WRITE_DATA = data ;
|
|
|
$display(" bridge target - Setting base address P_BA1 to 32'h %h !", data);
|
$display(" bridge target - Setting base address P_BA1 to 32'h %h !", data);
|
wishbone_master.wb_single_write( write_data, write_flags, write_status ) ;
|
wishbone_master.wb_single_write( write_data, write_flags, write_status ) ;
|
if ( write_status`CYC_ACTUAL_TRANSFER !== 1 )
|
if ( write_status`CYC_ACTUAL_TRANSFER !== 1 )
|
| Line 12649... |
Line 12672... |
offset = {4'h1, `P_BA2_ADDR, 2'b00} ; // PCI Base Address 2
|
offset = {4'h1, `P_BA2_ADDR, 2'b00} ; // PCI Base Address 2
|
data = Target_Base_Addr_R[2] ; // `TAR0_BASE_ADDR_2 = 32'h3000_0000
|
data = Target_Base_Addr_R[2] ; // `TAR0_BASE_ADDR_2 = 32'h3000_0000
|
|
|
write_data`WRITE_ADDRESS = temp_var + offset ;
|
write_data`WRITE_ADDRESS = temp_var + offset ;
|
write_data`WRITE_SEL = 4'hf ;
|
write_data`WRITE_SEL = 4'hf ;
|
write_data`WRITE_TAG_STIM = 0 ;
|
|
write_data`WRITE_DATA = data ;
|
write_data`WRITE_DATA = data ;
|
|
|
$display(" bridge target - Setting base address P_BA2 to 32'h %h !", data);
|
$display(" bridge target - Setting base address P_BA2 to 32'h %h !", data);
|
wishbone_master.wb_single_write( write_data, write_flags, write_status ) ;
|
wishbone_master.wb_single_write( write_data, write_flags, write_status ) ;
|
if ( write_status`CYC_ACTUAL_TRANSFER !== 1 )
|
if ( write_status`CYC_ACTUAL_TRANSFER !== 1 )
|
| Line 12665... |
Line 12687... |
offset = {4'h1, `P_BA3_ADDR, 2'b00} ; // PCI Base Address 3
|
offset = {4'h1, `P_BA3_ADDR, 2'b00} ; // PCI Base Address 3
|
data = Target_Base_Addr_R[3] ; // `TAR0_BASE_ADDR_3 = 32'h4000_0000
|
data = Target_Base_Addr_R[3] ; // `TAR0_BASE_ADDR_3 = 32'h4000_0000
|
|
|
write_data`WRITE_ADDRESS = temp_var + offset ;
|
write_data`WRITE_ADDRESS = temp_var + offset ;
|
write_data`WRITE_SEL = 4'hf ;
|
write_data`WRITE_SEL = 4'hf ;
|
write_data`WRITE_TAG_STIM = 0 ;
|
|
write_data`WRITE_DATA = data ;
|
write_data`WRITE_DATA = data ;
|
|
|
$display(" bridge target - Setting base address P_BA3 to 32'h %h !", data);
|
$display(" bridge target - Setting base address P_BA3 to 32'h %h !", data);
|
wishbone_master.wb_single_write( write_data, write_flags, write_status ) ;
|
wishbone_master.wb_single_write( write_data, write_flags, write_status ) ;
|
if ( write_status`CYC_ACTUAL_TRANSFER !== 1 )
|
if ( write_status`CYC_ACTUAL_TRANSFER !== 1 )
|
| Line 12681... |
Line 12702... |
offset = {4'h1, `P_BA4_ADDR, 2'b00} ; // PCI Base Address 4
|
offset = {4'h1, `P_BA4_ADDR, 2'b00} ; // PCI Base Address 4
|
data = Target_Base_Addr_R[4] ; // `TAR0_BASE_ADDR_4 = 32'h5000_0000
|
data = Target_Base_Addr_R[4] ; // `TAR0_BASE_ADDR_4 = 32'h5000_0000
|
|
|
write_data`WRITE_ADDRESS = temp_var + offset ;
|
write_data`WRITE_ADDRESS = temp_var + offset ;
|
write_data`WRITE_SEL = 4'hf ;
|
write_data`WRITE_SEL = 4'hf ;
|
write_data`WRITE_TAG_STIM = 0 ;
|
|
write_data`WRITE_DATA = data ;
|
write_data`WRITE_DATA = data ;
|
|
|
$display(" bridge target - Setting base address P_BA4 to 32'h %h !", data);
|
$display(" bridge target - Setting base address P_BA4 to 32'h %h !", data);
|
wishbone_master.wb_single_write( write_data, write_flags, write_status ) ;
|
wishbone_master.wb_single_write( write_data, write_flags, write_status ) ;
|
if ( write_status`CYC_ACTUAL_TRANSFER !== 1 )
|
if ( write_status`CYC_ACTUAL_TRANSFER !== 1 )
|
| Line 12697... |
Line 12717... |
offset = {4'h1, `P_BA5_ADDR, 2'b00} ; // PCI Base Address 5
|
offset = {4'h1, `P_BA5_ADDR, 2'b00} ; // PCI Base Address 5
|
data = Target_Base_Addr_R[5] ; // `TAR0_BASE_ADDR_5 = 32'h6000_0000
|
data = Target_Base_Addr_R[5] ; // `TAR0_BASE_ADDR_5 = 32'h6000_0000
|
|
|
write_data`WRITE_ADDRESS = temp_var + offset ;
|
write_data`WRITE_ADDRESS = temp_var + offset ;
|
write_data`WRITE_SEL = 4'hf ;
|
write_data`WRITE_SEL = 4'hf ;
|
write_data`WRITE_TAG_STIM = 0 ;
|
|
write_data`WRITE_DATA = data ;
|
write_data`WRITE_DATA = data ;
|
|
|
$display(" bridge target - Setting base address P_BA5 to 32'h %h !", data);
|
$display(" bridge target - Setting base address P_BA5 to 32'h %h !", data);
|
wishbone_master.wb_single_write( write_data, write_flags, write_status ) ;
|
wishbone_master.wb_single_write( write_data, write_flags, write_status ) ;
|
if ( write_status`CYC_ACTUAL_TRANSFER !== 1 )
|
if ( write_status`CYC_ACTUAL_TRANSFER !== 1 )
|
| Line 19168... |
Line 19187... |
write_flags`WB_TRANSFER_AUTO_RTY = 1'b0 ;
|
write_flags`WB_TRANSFER_AUTO_RTY = 1'b0 ;
|
|
|
// initiate a read request
|
// initiate a read request
|
read_data`READ_ADDRESS = target_address ;
|
read_data`READ_ADDRESS = target_address ;
|
read_data`READ_SEL = 4'hF ;
|
read_data`READ_SEL = 4'hF ;
|
read_data`READ_TAG_STIM = 0 ;
|
|
wishbone_master.wb_single_read( read_data, write_flags, read_status ) ;
|
wishbone_master.wb_single_read( read_data, write_flags, read_status ) ;
|
if ((read_status`CYC_ACTUAL_TRANSFER !== 0) || (read_status`CYC_RTY !== 1'b1))
|
if ((read_status`CYC_ACTUAL_TRANSFER !== 0) || (read_status`CYC_RTY !== 1'b1))
|
begin
|
begin
|
$display("Completion expiration testing failed! Bridge failed to process single memory read! Time %t ", $time) ;
|
$display("Completion expiration testing failed! Bridge failed to process single memory read! Time %t ", $time) ;
|
test_fail("PCI bridge didn't process the read as expected - didn't respond with retry");
|
test_fail("PCI bridge didn't process the read as expected - didn't respond with retry");
|
| Line 19199... |
Line 19217... |
@(posedge wb_clock) ;
|
@(posedge wb_clock) ;
|
|
|
// now perform a read
|
// now perform a read
|
read_data`READ_ADDRESS = target_address + 4 ;
|
read_data`READ_ADDRESS = target_address + 4 ;
|
read_data`READ_SEL = 4'hF ;
|
read_data`READ_SEL = 4'hF ;
|
read_data`READ_TAG_STIM = 0 ;
|
|
wishbone_master.wb_single_read( read_data, write_flags, read_status ) ;
|
wishbone_master.wb_single_read( read_data, write_flags, read_status ) ;
|
if (read_status`CYC_ACTUAL_TRANSFER !== 1)
|
if (read_status`CYC_ACTUAL_TRANSFER !== 1)
|
begin
|
begin
|
$display("Completion expiration testing failed! Bridge failed to process single memory read! Time %t ", $time) ;
|
$display("Completion expiration testing failed! Bridge failed to process single memory read! Time %t ", $time) ;
|
test_fail("PCI bridge didn't process the read as expected");
|
test_fail("PCI bridge didn't process the read as expected");
|
| Line 19305... |
Line 19322... |
|
|
temp_var = { `WB_CONFIGURATION_BASE, 12'h000 } ;
|
temp_var = { `WB_CONFIGURATION_BASE, 12'h000 } ;
|
temp_var[(31 - `WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
|
temp_var[(31 - `WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
|
write_data`WRITE_ADDRESS = temp_var + offset ;
|
write_data`WRITE_ADDRESS = temp_var + offset ;
|
write_data`WRITE_SEL = byte_enable ;
|
write_data`WRITE_SEL = byte_enable ;
|
write_data`WRITE_TAG_STIM = 0 ;
|
|
write_data`WRITE_DATA = data ;
|
write_data`WRITE_DATA = data ;
|
|
|
wishbone_master.wb_single_write( write_data, write_flags, write_status ) ;
|
wishbone_master.wb_single_write( write_data, write_flags, write_status ) ;
|
if ( write_status`CYC_ACTUAL_TRANSFER !== 1 )
|
if ( write_status`CYC_ACTUAL_TRANSFER !== 1 )
|
begin
|
begin
|
| Line 19390... |
Line 19406... |
temp_var = { `WB_CONFIGURATION_BASE, 12'h000 } ;
|
temp_var = { `WB_CONFIGURATION_BASE, 12'h000 } ;
|
temp_var[(31 - `WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
|
temp_var[(31 - `WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
|
|
|
read_data`READ_ADDRESS = temp_var + offset ;
|
read_data`READ_ADDRESS = temp_var + offset ;
|
read_data`READ_SEL = byte_enable ;
|
read_data`READ_SEL = byte_enable ;
|
read_data`READ_TAG_STIM = 0 ;
|
|
|
|
wishbone_master.wb_single_read( read_data, read_flags, read_status ) ;
|
wishbone_master.wb_single_read( read_data, read_flags, read_status ) ;
|
if (read_status`CYC_ACTUAL_TRANSFER !== 1)
|
if (read_status`CYC_ACTUAL_TRANSFER !== 1)
|
begin
|
begin
|
$display("Configuration read failed! Bridge failed to process single memory read! Time %t ", $time) ;
|
$display("Configuration read failed! Bridge failed to process single memory read! Time %t ", $time) ;
|
| Line 20073... |
Line 20088... |
begin
|
begin
|
|
|
// do one dummy read, to receive bus gnt
|
// do one dummy read, to receive bus gnt
|
read_data`READ_ADDRESS = target_address ;
|
read_data`READ_ADDRESS = target_address ;
|
read_data`READ_SEL = 4'hF ;
|
read_data`READ_SEL = 4'hF ;
|
read_data`READ_TAG_STIM = 0 ;
|
|
|
|
// handle retries
|
// handle retries
|
flags`WB_TRANSFER_AUTO_RTY = 1 ;
|
flags`WB_TRANSFER_AUTO_RTY = 1 ;
|
|
|
wishbone_master.wb_single_read( read_data, flags, read_status ) ;
|
wishbone_master.wb_single_read( read_data, flags, read_status ) ;
|
| Line 20114... |
Line 20128... |
end
|
end
|
|
|
// read data back
|
// read data back
|
read_data`READ_ADDRESS = target_address + 64 ;
|
read_data`READ_ADDRESS = target_address + 64 ;
|
read_data`READ_SEL = 4'hF ;
|
read_data`READ_SEL = 4'hF ;
|
read_data`READ_TAG_STIM = 0 ;
|
|
|
|
// handle retries
|
// handle retries
|
flags`WB_TRANSFER_AUTO_RTY = 1 ;
|
flags`WB_TRANSFER_AUTO_RTY = 1 ;
|
|
|
wishbone_master.wb_single_read( read_data, flags, read_status ) ;
|
wishbone_master.wb_single_read( read_data, flags, read_status ) ;
|
| Line 20137... |
Line 20150... |
end
|
end
|
|
|
// read second data back
|
// read second data back
|
read_data`READ_ADDRESS = target_address + 128 ;
|
read_data`READ_ADDRESS = target_address + 128 ;
|
read_data`READ_SEL = 4'hF ;
|
read_data`READ_SEL = 4'hF ;
|
read_data`READ_TAG_STIM = 0 ;
|
|
|
|
// handle retries
|
// handle retries
|
flags`WB_TRANSFER_AUTO_RTY = 1 ;
|
flags`WB_TRANSFER_AUTO_RTY = 1 ;
|
|
|
wishbone_master.wb_single_read( read_data, flags, read_status ) ;
|
wishbone_master.wb_single_read( read_data, flags, read_status ) ;
|
| Line 20434... |
Line 20446... |
test_ok ;
|
test_ok ;
|
end
|
end
|
endtask // test_target_overload
|
endtask // test_target_overload
|
|
|
task test_master_overload ;
|
task test_master_overload ;
|
|
|
reg ok_pci ;
|
reg ok_pci ;
|
reg ok_wb ;
|
reg ok_wb ;
|
reg ok ;
|
reg ok ;
|
reg [2:0] test_image_num ;
|
reg [2:0] test_image_num ;
|
integer transfered ;
|
|
reg [2:0] received_termination ;
|
reg [2:0] received_termination ;
|
integer total_transfers ;
|
|
reg [31:0] transaction_sizes [0:4095] ;
|
reg [31:0] transaction_sizes [0:4095] ;
|
integer pci_transaction_num ;
|
|
integer wb_transaction_num ;
|
|
reg [31:0] current_pci_address ;
|
|
integer current_size ;
|
|
|
|
reg `WRITE_STIM_TYPE write_data ;
|
reg `WRITE_STIM_TYPE write_data ;
|
|
|
reg `WRITE_RETURN_TYPE write_status ;
|
reg `WRITE_RETURN_TYPE write_status ;
|
reg `WB_TRANSFER_FLAGS write_flags ;
|
reg `WB_TRANSFER_FLAGS write_flags ;
|
|
|
reg [31:0] image_base ;
|
reg [31:0] image_base ;
|
reg [31:0] target_address ;
|
reg [31:0] target_address ;
|
|
|
integer i ;
|
|
integer j ;
|
|
integer k ;
|
|
integer l ;
|
|
begin:main
|
begin:main
|
|
|
// set behavioral target to respond normally
|
// set behavioral target to respond normally
|
test_target_response[`TARGET_ENCODED_TERMINATION] = `Test_Target_Normal_Completion ;
|
test_target_response[`TARGET_ENCODED_TERMINATION] = `Test_Target_Normal_Completion ;
|
test_target_response[`TARGET_ENCODED_TERMINATE_ON] = 0 ;
|
test_target_response[`TARGET_ENCODED_TERMINATE_ON] = 0 ;
|
| Line 20497... |
Line 20500... |
write_flags = 0 ;
|
write_flags = 0 ;
|
write_flags`INIT_WAITS = wb_init_waits ;
|
write_flags`INIT_WAITS = wb_init_waits ;
|
write_flags`SUBSEQ_WAITS = wb_subseq_waits ;
|
write_flags`SUBSEQ_WAITS = wb_subseq_waits ;
|
write_flags`WB_TRANSFER_AUTO_RTY = 0 ;
|
write_flags`WB_TRANSFER_AUTO_RTY = 0 ;
|
write_flags`WB_TRANSFER_CAB = 1'b1 ;
|
write_flags`WB_TRANSFER_CAB = 1'b1 ;
|
write_flags`WB_FAST_B2B = 1'b1 ;
|
|
|
|
pci_configure_wb_slave_image
|
pci_configure_wb_slave_image
|
(
|
(
|
1'b1, // use_bus
|
1'b1, // use_bus
|
test_image_num, // image_num
|
test_image_num, // image_num
|
| Line 20522... |
Line 20524... |
end
|
end
|
|
|
ok_wb = 1 ;
|
ok_wb = 1 ;
|
ok_pci = 1 ;
|
ok_pci = 1 ;
|
|
|
total_transfers = 0 ;
|
fork
|
|
begin:wb_write_overflow_blk
|
|
integer current_write_size ;
|
|
integer total_wb_transfers ;
|
|
reg [11:0] wb_transaction_num ;
|
|
integer i ;
|
|
|
for (current_size = 1 ; (current_size <= 1024) && ok_pci && ok_wb && ok ; current_size = current_size * 2)
|
wb_transaction_num = 0 ;
|
|
transaction_sizes[wb_transaction_num[11:0]] = 0 ;
|
|
|
|
for (current_write_size = 1 ; (current_write_size <= 1024) & ok_pci & ok_wb & ok ; current_write_size = current_write_size * 2)
|
begin
|
begin
|
|
|
// fill wishbone master's memory with data - inverted addresses
|
// fill wishbone master's memory with data - inverted addresses
|
write_data = 0 ;
|
write_data = 0 ;
|
write_data`WRITE_SEL = 4'hF ;
|
write_data`WRITE_SEL = 4'hF ;
|
for (i = 0 ; i < current_size ; i = i + 1)
|
for (i = 0 ; i < current_write_size ; i = i + 1)
|
begin
|
begin
|
write_data`WRITE_ADDRESS = image_base + ((('d1024 - current_size) * 4) + (i * 4)) ;
|
write_data`WRITE_ADDRESS = image_base + ((('d1024 - current_write_size) * 4) + (i * 4)) ;
|
write_data`WRITE_DATA = ~(write_data`WRITE_ADDRESS);
|
write_data`WRITE_DATA = ~(write_data`WRITE_ADDRESS);
|
wishbone_master.blk_write_data[i] = write_data ;
|
wishbone_master.blk_write_data[i] = write_data ;
|
end
|
end
|
|
|
total_transfers = 0 ;
|
total_wb_transfers = 0 ;
|
pci_transaction_num = 0 ;
|
|
wb_transaction_num = 0 ;
|
|
|
|
current_pci_address = image_base + ('d1024 - current_size) * 4 ;
|
write_flags`WB_FAST_B2B = 1'b0 ;
|
fork
|
|
begin
|
while ((total_wb_transfers < current_write_size) & ok_pci & ok_wb & ok)
|
while ((total_transfers < current_size) && ok_pci && ok_wb && ok)
|
|
begin
|
begin
|
// try transfering 4kB with no wait cycles through the wb slave unit
|
|
write_flags`WB_TRANSFER_SIZE = current_size - total_transfers ;
|
write_flags`WB_TRANSFER_SIZE = current_write_size - total_wb_transfers ;
|
wishbone_master.wb_block_write(write_flags, write_status) ;
|
wishbone_master.wb_block_write(write_flags, write_status) ;
|
if (write_status`CYC_ERR || ((write_status`CYC_ERR !== 1'b1) && (write_status`CYC_RTY !== 1'b1) && (write_status`CYC_ACK !== 1'b1)))
|
write_flags`WB_FAST_B2B = 1'b1 ;
|
|
|
|
if (write_status`CYC_ERR | ((write_status`CYC_ERR !== 1'b1) & (write_status`CYC_RTY !== 1'b1) & (write_status`CYC_ACK !== 1'b1)))
|
begin
|
begin
|
|
$display("%m detected an error!") ;
|
test_fail("Wishbone slave signaled an error or did not respond to normal write access") ;
|
test_fail("Wishbone slave signaled an error or did not respond to normal write access") ;
|
ok_wb = 0 ;
|
ok_wb = 0 ;
|
end
|
end
|
|
|
transfered = write_status`CYC_ACTUAL_TRANSFER ;
|
total_wb_transfers = total_wb_transfers + write_status`CYC_ACTUAL_TRANSFER ;
|
total_transfers = total_transfers + transfered ;
|
|
if (transfered > 0)
|
if (write_status`CYC_ACTUAL_TRANSFER > 0)
|
begin
|
begin
|
transaction_sizes[wb_transaction_num[11:0]] = transfered ;
|
transaction_sizes[wb_transaction_num[11:0]] = write_status`CYC_ACTUAL_TRANSFER ;
|
wishbone_master.shift_write_buffer(transfered) ;
|
wishbone_master.shift_write_buffer(write_status`CYC_ACTUAL_TRANSFER) ;
|
|
|
wb_transaction_num = wb_transaction_num + 1'b1 ;
|
wb_transaction_num = wb_transaction_num + 1'b1 ;
|
|
transaction_sizes[wb_transaction_num[11:0]] = 0 ;
|
|
|
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
begin:pci_models_monitoring
|
begin:pci_models_monitoring
|
while (((total_transfers < current_size) || (wb_transaction_num > pci_transaction_num)) && ok_pci && ok_wb && ok)
|
reg [31:0] ret_adr ; reg [3:0] ret_bc ; integer ret_num_of_transfers ; integer total_ret_num_of_transfers ;
|
|
reg ret_gnt_deasserted ;
|
|
integer current_write_size ; reg [11:0] pci_transaction_num ; reg [31:0] current_pci_address ;
|
|
integer i ;
|
|
|
|
pci_transaction_num = 0 ;
|
|
|
|
for (current_write_size = 1 ; (current_write_size <= 1024) & ok_pci & ok_wb & ok ; current_write_size = current_write_size * 2)
|
begin
|
begin
|
wait(wb_transaction_num > pci_transaction_num) ;
|
|
pci_transaction_progress_monitor
|
current_pci_address = image_base + ('d1024 - current_write_size) * 4 ;
|
(
|
|
current_pci_address, // address
|
total_ret_num_of_transfers = 0 ;
|
`BC_MEM_WRITE, // bus_command
|
|
transaction_sizes[pci_transaction_num[11:0]], // num_of_transfers
|
while ( (total_ret_num_of_transfers < current_write_size) & ok_pci & ok_wb & ok )
|
0, // num_of_cycles
|
begin
|
1'b1, // check_transfers
|
monitor32.get_pci_op(ret_adr, ret_bc) ;
|
1'b0, // check_cycles
|
monitor32.get_pci_op_num_of_transfers(ret_num_of_transfers, ret_gnt_deasserted) ;
|
1'b0, // doing_fast_back_to_back
|
|
ok_pci // ok
|
wait( transaction_sizes[pci_transaction_num[11:0]] > 0) ;
|
) ;
|
|
|
if (ret_adr !== current_pci_address)
|
|
begin
|
|
$display("%m detected an error!") ;
|
|
test_fail("PCI Master provided unexpected address when it initiated write operation") ;
|
|
ok_pci = 1'b0 ;
|
|
end
|
|
|
|
if (ret_bc !== `BC_MEM_WRITE)
|
|
begin
|
|
$display("%m detected an error!") ;
|
|
test_fail("PCI Master provided unexpected bus command when it should initiate write operation") ;
|
|
ok_pci = 1'b0 ;
|
|
end
|
|
|
|
if (ret_num_of_transfers !== transaction_sizes[pci_transaction_num[11:0]])
|
|
begin
|
|
$display("%m detected an error!") ;
|
|
test_fail("PCI Master didn't transfer expected number of words during a burst transfer") ;
|
|
ok_pci = 1'b0 ;
|
|
end
|
|
|
|
total_ret_num_of_transfers = total_ret_num_of_transfers + ret_num_of_transfers ;
|
|
|
current_pci_address = current_pci_address + (4 * transaction_sizes[pci_transaction_num[11:0]]) ;
|
current_pci_address = current_pci_address + (4 * transaction_sizes[pci_transaction_num[11:0]]) ;
|
pci_transaction_num = pci_transaction_num + 1'b1 ;
|
pci_transaction_num = pci_transaction_num + 1'b1 ;
|
if (ok_pci !== 1'b1)
|
end
|
|
|
|
// check the written data
|
|
@(posedge pci_clock) ;
|
|
#1 ;
|
|
for (i = 0 ; i < current_write_size ; i = i + 1)
|
|
begin:data_chk_blk
|
|
reg [31:0] exp_dat ; reg [31:0] act_dat ;
|
|
|
|
exp_dat = image_base + ((('d1024 - current_write_size) * 4) + (i * 4)) ;
|
|
exp_dat = ~exp_dat ;
|
|
act_dat = pci_behaviorial_device1.pci_behaviorial_target.Test_Device_Mem['d1024 - current_write_size + i] ;
|
|
if (exp_dat != act_dat)
|
begin
|
begin
|
test_fail("PCI Transaction progress monitor detected invalid transaction or none at all on PCI bus");
|
$display("Time %t!", $time) ;
|
|
$display("Wrong data written to the target detected! Expected data %h, actual %h", exp_dat, act_dat) ;
|
|
test_fail("wrong data was written to the target during the test") ;
|
|
ok_pci = 0 ;
|
|
disable main ;
|
|
end
|
end
|
end
|
end
|
end
|
|
|
// wait two cycles for any wrong parity errors etc..
|
// wait two cycles for any wrong parity errors etc..
|
repeat (2)
|
repeat (2)
|
| Line 20606... |
Line 20665... |
ok_pci = 0 ;
|
ok_pci = 0 ;
|
ok_wb = 0 ;
|
ok_wb = 0 ;
|
end
|
end
|
join
|
join
|
|
|
// check the written data
|
if ((ok & ok_wb & ok_pci) === 1'b1)
|
for (i = 0 ; i < current_size ; i = i + 1)
|
test_ok ;
|
begin
|
|
write_data`WRITE_ADDRESS = image_base + ((('d1024 - current_size) * 4) + (i * 4)) ;
|
|
write_data`WRITE_DATA = ~(write_data`WRITE_ADDRESS);
|
|
write_data`WRITE_ADDRESS = pci_behaviorial_device1.pci_behaviorial_target.Test_Device_Mem['d1024 - current_size + i] ;
|
|
if (write_data`WRITE_ADDRESS != write_data`WRITE_DATA)
|
|
begin
|
|
$display("Time %t!", $time) ;
|
|
$display("Wrong data written to the target detected! Expected data %h, actual %h", write_data`WRITE_DATA, write_data`WRITE_ADDRESS) ;
|
|
test_fail("wrong data was written to the target during the test") ;
|
|
disable main ;
|
|
end
|
|
end
|
|
end
|
|
|
|
|
|
// next two tests take forever - commented out - they are here, because some bugs were reported
|
// next two tests take forever - commented out - they are here, because some bugs were reported
|
// they are commented out, because no bug could be found with them
|
// they are commented out, because no bug could be found with them
|
/*
|
/*
|
total_transfers = 0 ;
|
total_transfers = 0 ;
|
| Line 20847... |
Line 20892... |
if (ok !== 1'b1)
|
if (ok !== 1'b1)
|
begin
|
begin
|
test_fail("WB image configuration failed") ;
|
test_fail("WB image configuration failed") ;
|
disable main ;
|
disable main ;
|
end
|
end
|
|
|
if ((ok && ok_wb && ok_pci) === 1'b1)
|
|
test_ok ;
|
|
end
|
end
|
endtask // test_master_overload
|
endtask // test_master_overload
|
|
|
|
`ifdef fofofof
|
|
`ifdef PCI_WB_REV_B3
|
|
`ifdef PCI_WBS_B3_RTY_DISABLE
|
|
task test_wb_slave_with_retry_generation_disabled ;
|
|
reg [11:0] ctrl_offset ;
|
|
reg [11:0] ba_offset ;
|
|
reg [11:0] am_offset ;
|
|
reg `WRITE_STIM_TYPE write_data ;
|
|
reg `READ_STIM_TYPE read_data ;
|
|
reg `READ_RETURN_TYPE read_status ;
|
|
|
|
reg `WRITE_RETURN_TYPE write_status ;
|
|
reg `WB_TRANSFER_FLAGS flags ;
|
|
reg wb_ok ;
|
|
reg pci_ok ;
|
|
reg ok ;
|
|
reg [11:0] pci_ctrl_offset ;
|
|
reg [11:0] cl_size_offset ;
|
|
reg [3:0] cl_size_mask ;
|
|
reg [31:0] image_base ;
|
|
reg [31:0] target_address ;
|
|
|
|
integer i ;
|
|
reg [2:0] cur_inc_burst_type ;
|
|
|
|
begin:main
|
|
wb_ok = 1'b0 ;
|
|
pci_ok = 1'b0 ;
|
|
ok = 1'b0 ;
|
|
|
|
test_name = "CONFIGURE WB IMAGE 1 FOR WB SLAVE WITH NO RETRY RESPONSE TESTING" ;
|
|
|
|
pci_ctrl_offset = 12'h4 ;
|
|
|
|
// image 0 can only be configuration image - start with 1
|
|
ctrl_offset = {4'h1, `W_IMG_CTRL1_ADDR, 2'b00} ;
|
|
ba_offset = {4'h1, `W_BA1_ADDR, 2'b00} ;
|
|
am_offset = {4'h1, `W_AM1_ADDR, 2'b00} ;
|
|
cl_size_offset = 12'hC ;
|
|
cl_size_mask = 4'b0001 ;
|
|
|
|
target_address = `BEH_TAR1_MEM_START ;
|
|
image_base = 0 ;
|
|
image_base[`PCI_BASE_ADDR0_MATCH_RANGE] = target_address[`PCI_BASE_ADDR0_MATCH_RANGE] ;
|
|
|
|
target_address[31:(32 - `WB_NUM_OF_DEC_ADDR_LINES)] = image_base[31:(32 - `WB_NUM_OF_DEC_ADDR_LINES)] ;
|
|
target_address[(31 - `WB_NUM_OF_DEC_ADDR_LINES):0] = image_base[(31 - `WB_NUM_OF_DEC_ADDR_LINES):0] ;
|
|
write_flags = 0 ;
|
|
write_flags`INIT_WAITS = wb_init_waits ;
|
|
write_flags`SUBSEQ_WAITS = wb_subseq_waits ;
|
|
write_flags`WB_TRANSFER_AUTO_RTY = 0 ;
|
|
|
|
// enable master & target operation
|
|
config_write( pci_ctrl_offset, 32'h0000_0007, 4'h1, ok) ;
|
|
if ( ok !== 1 )
|
|
begin
|
|
$display("No retry response testing failed! Failed to write PCI Device Control register! Time %t ", $time) ;
|
|
test_fail("write to PCI Device Control register didn't succeede");
|
|
disable main ;
|
|
end
|
|
|
|
// prepare image control register
|
|
config_write( ctrl_offset, 32'h0000_0000, 4'hF, ok) ;
|
|
if ( ok !== 1 )
|
|
begin
|
|
$display("No retry response testing failed! Failed to write W_IMG_CTRL%d register! Time %t ", 1, $time) ;
|
|
test_fail("write to WB Image Control register didn't succeede");
|
|
disable main ;
|
|
end
|
|
|
|
// prepare base address register
|
|
config_write( ba_offset, image_base, 4'hF, ok ) ;
|
|
if ( ok !== 1 )
|
|
begin
|
|
$display("No retry response testing failed! Failed to write W_BA%d register! Time %t ", 1, $time) ;
|
|
test_fail("write to WB Base Address register didn't succeede");
|
|
disable main ;
|
|
end
|
|
|
|
// write address mask register
|
|
config_write( am_offset, 32'hFFFF_FFFF, 4'hF, ok ) ;
|
|
if ( ok !== 1 )
|
|
begin
|
|
$display("No retry response testing failed! Failed to write W_AM%d register! Time %t ", 1, $time) ;
|
|
test_fail("write to WB Address Mask register didn't succeede");
|
|
disable main ;
|
|
end
|
|
|
|
// write cache line size register
|
|
config_write( cl_size_offset, 32'h4, cl_size_mask, ok ) ;
|
|
if ( ok !== 1 )
|
|
begin
|
|
$display("No retry response testing failed! Failed to write CACHE LINE SIZE register! Time %t ", $time) ;
|
|
test_fail("write to CACHE LINE SIZE register didn't succeede");
|
|
disable main ;
|
|
end
|
|
|
|
for (cur_inc_burst_type = 0 ; cur_inc_burst_type <= 3 ; cur_inc_burst_type = cur_inc_burst_type + 1'b1)
|
|
begin
|
|
// prepare write data - prepare enough to fill at least 2 write fifos.
|
|
for (i = 0 ; i < ((`PCIW_DEPTH) * 2) ; i = i + 1)
|
|
begin
|
|
write_data`WRITE_DATA = $random ;
|
|
|
|
case (cur_inc_burst_type)
|
|
2'b00:
|
|
begin
|
|
write_data`WRITE_ADDRESS = image_base + i * 4 + 'd8 ;
|
|
end
|
|
2'b01:
|
|
begin
|
|
write_data`WRITE_ADDRESS = ( image_base[31:4] + (i >> 2) ) << 4 ;
|
|
if ( (i % 4) === 0 )
|
|
write_data`WRITE_ADDRESS = write_data`WRITE_ADDRESS + 'd8 ;
|
|
else
|
|
write_data`WRITE_ADDRESS = write_data`WRITE_ADDRESS + (4'd8 + (i * 4 % 4) ;
|
|
end
|
|
2'b10:
|
|
begin
|
|
end
|
|
2'b11:
|
|
begin
|
|
end
|
|
endcase
|
|
|
|
if (cur_inc_burst_type === 0)
|
|
write_data`WRITE_ADDRESS = image_base + i * 4 + 4 ;
|
|
|
|
if ( (i % 4) === 0)
|
|
write_data`WRITE_ADDRESS = {image_base[31:4] + (i >> 2), 4'h4}
|
|
end
|
|
|
|
fork
|
|
begin
|
|
// perform a write with auto retry off, since retries should not be signalled by wishbone slave
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|
flags`WB_TRANSFER_AUTO_RETRY = 1'b0 ;
|
|
|
|
// check if received termination is not retry nor error
|
|
|
|
// check if all transfers completed succesfully!
|
|
|
|
end
|
|
begin
|
|
|
|
// set behavioral target to respond with retry
|
|
|
|
// check 2 transactions terminated with retry
|
|
|
|
// set behavioral target to disconnect with data on first transfer
|
|
// check the transaction
|
|
|
|
end
|
|
join
|
|
end
|
|
end
|
|
endtask // test_wb_slave_with_retry_generation_disabled
|
|
`endif
|
|
`endif
|
|
`endif
|
|
|
task test_fail ;
|
task test_fail ;
|
input [7999:0] failure_reason ;
|
input [7999:0] failure_reason ;
|
reg [8007:0] display_failure ;
|
|
reg [799:0] display_test ;
|
|
begin
|
begin
|
tests_failed = tests_failed + 1 ;
|
tests_failed = tests_failed + 1 ;
|
|
|
display_failure = {failure_reason, "!"} ;
|
|
while ( display_failure[7999:7992] == 0 )
|
|
display_failure = display_failure << 8 ;
|
|
|
|
display_test = test_name ;
|
|
while ( display_test[799:792] == 0 )
|
|
display_test = display_test << 8 ;
|
|
|
|
$fdisplay( tb_log_file, "************************************************************************************************************************************************************" ) ;
|
$fdisplay( tb_log_file, "************************************************************************************************************************************************************" ) ;
|
$fdisplay( tb_log_file, " At time %t ", $time ) ;
|
$fdisplay( tb_log_file, " At time %t ", $time ) ;
|
$fdisplay( tb_log_file, " Test %s", display_test ) ;
|
$fdisplay( tb_log_file, " Test %0s", test_name ) ;
|
$fdisplay( tb_log_file, " *FAILED* because") ;
|
$fdisplay( tb_log_file, " *FAILED* because") ;
|
$fdisplay( tb_log_file, " %s", display_failure ) ;
|
$fdisplay( tb_log_file, " %0s", failure_reason) ;
|
current_test_parameters ;
|
current_test_parameters ;
|
$fdisplay( tb_log_file, "************************************************************************************************************************************************************" ) ;
|
$fdisplay( tb_log_file, "************************************************************************************************************************************************************" ) ;
|
$fdisplay( tb_log_file, " " ) ;
|
$fdisplay( tb_log_file, " " ) ;
|
|
|
`ifdef STOP_ON_FAILURE
|
`ifdef STOP_ON_FAILURE
|
| Line 20884... |
Line 21076... |
`endif
|
`endif
|
end
|
end
|
endtask // test_fail
|
endtask // test_fail
|
|
|
task test_ok ;
|
task test_ok ;
|
reg [799:0] display_test ;
|
|
begin
|
begin
|
tests_successfull = tests_successfull + 1 ;
|
tests_successfull = tests_successfull + 1 ;
|
|
|
display_test = test_name ;
|
|
while ( display_test[799:792] == 0 )
|
|
display_test = display_test << 8 ;
|
|
|
|
$fdisplay( tb_log_file, "************************************************************************************************************************************************************" ) ;
|
$fdisplay( tb_log_file, "************************************************************************************************************************************************************" ) ;
|
$fdisplay( tb_log_file, " At time %t ", $time ) ;
|
$fdisplay( tb_log_file, " At time %t ", $time ) ;
|
$fdisplay( tb_log_file, " Test %s", display_test ) ;
|
$fdisplay( tb_log_file, " Test %0s", test_name ) ;
|
$fdisplay( tb_log_file, " reported *SUCCESSFULL*! ") ;
|
$fdisplay( tb_log_file, " reported *SUCCESSFULL*! ") ;
|
current_test_parameters ;
|
current_test_parameters ;
|
$fdisplay( tb_log_file, "************************************************************************************************************************************************************" ) ;
|
$fdisplay( tb_log_file, "************************************************************************************************************************************************************" ) ;
|
$fdisplay( tb_log_file, " " ) ;
|
$fdisplay( tb_log_file, " " ) ;
|
end
|
end
|
