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Line 41... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2002/02/01 13:39:43 mihad
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// Initial testbench import. Still under development
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//
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// Revision 1.1 2001/08/06 18:12:58 mihad
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// Revision 1.1 2001/08/06 18:12:58 mihad
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// Pocasi delamo kompletno zadevo
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// Pocasi delamo kompletno zadevo
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//
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//
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//
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//
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| Line 153... |
Line 156... |
end
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end
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reg [`WB_DATA_WIDTH-1:0] previous_data ;
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reg [`WB_DATA_WIDTH-1:0] previous_data ;
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reg [`WB_ADDR_WIDTH-1:0] previous_address ;
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reg [`WB_ADDR_WIDTH-1:0] previous_address ;
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reg [`WB_SEL_WIDTH-1:0] previous_sel ;
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reg [`WB_SEL_WIDTH-1:0] previous_sel ;
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reg previous_stb ;
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reg previous_ack ;
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reg previous_err ;
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reg previous_rty ;
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reg previous_cyc ;
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reg can_change ;
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reg can_change ;
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// cycle monitor
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always@(posedge CLK_I or posedge RST_I)
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always@(posedge CLK_I or posedge RST_I)
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begin
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begin
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if (RST_I)
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begin
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previous_stb <= 1'b0 ;
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previous_ack <= 1'b0 ;
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previous_err <= 1'b0 ;
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previous_rty <= 1'b0 ;
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previous_cyc <= 1'b0 ;
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end
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else
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begin
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previous_stb <= STB_O ;
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previous_ack <= ACK_I ;
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previous_err <= ERR_I ;
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previous_rty <= RTY_I ;
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previous_cyc <= CYC_O ;
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end
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end
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// cycle monitor
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always@(posedge CLK_I)
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begin
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if (CYC_O && ~RST_I) // cycle in progress
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if (CYC_O && ~RST_I) // cycle in progress
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begin
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begin
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if (STB_O)
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if (STB_O)
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begin
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begin
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// check for two control signals active at same edge
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// check for two control signals active at same edge
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Line 253... |
begin
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begin
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$display("RTY_I asserted during cycle without STB_O") ;
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$display("RTY_I asserted during cycle without STB_O") ;
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$fdisplay(log_file_desc, "RTY_I asserted during cycle without STB_O") ;
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$fdisplay(log_file_desc, "RTY_I asserted during cycle without STB_O") ;
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end
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end
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if ((previous_ack !== 1) && (previous_err !== 1) && (previous_rty !== 1) && (previous_stb !== 0))
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begin
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$display("STB_O de-asserted without reception of slave response") ;
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$fdisplay(log_file_desc, "STB_O de-asserted without reception of slave response") ;
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end
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can_change = 1 ;
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can_change = 1 ;
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end // ~STB_O
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end // ~STB_O
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end // cycle in progress
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end // cycle in progress
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else if (!RST_I)
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begin
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// cycle not in progress anymore
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can_change = 1 ;
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if ((previous_ack !== 1) && (previous_err !== 1) && (previous_rty !== 1) && (previous_stb !== 0))
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begin
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$display("STB_O de-asserted without reception of slave response") ;
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$fdisplay(log_file_desc, "STB_O de-asserted without reception of slave response") ;
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end
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end
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end // cycle monitor
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end // cycle monitor
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// CAB_O monitor - CAB_O musn't change during one cycle
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// CAB_O monitor - CAB_O musn't change during one cycle
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reg [1:0] first_cab_val ;
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reg [1:0] first_cab_val ;
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always@(posedge CLK_I or RST_I)
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always@(posedge CLK_I or RST_I)
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