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[/] [pci/] [tags/] [rel_7/] [bench/] [verilog/] [wb_master32.v] - Diff between revs 92 and 104
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Rev 104 |
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2003/06/12 02:30:39 mihad
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// Update!
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//
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// Revision 1.1 2002/02/01 13:39:43 mihad
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// Revision 1.1 2002/02/01 13:39:43 mihad
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// Initial testbench import. Still under development
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// Initial testbench import. Still under development
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//
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//
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//
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//
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end
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end
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endtask //wbm_write
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endtask //wbm_write
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initial
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initial
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begin
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begin
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Tp = 1 / `WB_FREQ ;
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Tp = `WB_PERIOD ;
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in_use = 0 ;
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in_use = 0 ;
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cycle_in_progress = 0 ;
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cycle_in_progress = 0 ;
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cab = 0 ;
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cab = 0 ;
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ADR_O <= {`WB_ADDR_WIDTH{1'bx}} ;
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ADR_O <= {`WB_ADDR_WIDTH{1'bx}} ;
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DAT_O <= {`WB_DATA_WIDTH{1'bx}} ;
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DAT_O <= {`WB_DATA_WIDTH{1'bx}} ;
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