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Line 40... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2003/07/29 08:19:47 mihad
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// Found and simulated the problem in the synchronization logic.
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// Repaired the synchronization logic in the FIFOs.
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//
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// Revision 1.2 2003/06/12 02:30:39 mihad
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// Revision 1.2 2003/06/12 02:30:39 mihad
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// Update!
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// Update!
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//
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//
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// Revision 1.1 2002/02/01 13:39:43 mihad
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// Revision 1.1 2002/02/01 13:39:43 mihad
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// Initial testbench import. Still under development
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// Initial testbench import. Still under development
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Line 308... |
in_use = 1 ;
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in_use = 1 ;
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num_of_cyc = `WAIT_FOR_RESPONSE ;
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num_of_cyc = `WAIT_FOR_RESPONSE ;
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ADR_O <= #(Tp - `Tsetup) input_data`WRITE_ADDRESS ;
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ADR_O <= #(Tp - `Tsetup) input_data`WRITE_ADDRESS ;
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DAT_O <= #(Tp - `Tsetup) input_data`WRITE_DATA ;
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begin:dat_o_assign_blk
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reg [`WB_SEL_WIDTH - 1:0] cur_sel ;
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reg [`WB_DATA_WIDTH - 1:0] cur_dat ;
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reg [`WB_DATA_WIDTH - 1:0] rnd_dat ;
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integer cur_bit ;
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cur_dat = input_data`WRITE_DATA ;
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cur_sel = input_data`WRITE_SEL ;
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rnd_dat = $random ;
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for(cur_bit = 0 ; cur_bit < `WB_DATA_WIDTH ; cur_bit = cur_bit + 1)
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begin
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if (cur_sel[cur_bit/8] === 1'b1)
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DAT_O[cur_bit] <= #(Tp - `Tsetup) cur_dat[cur_bit] ;
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else
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DAT_O[cur_bit] <= #(Tp - `Tsetup) rnd_dat[cur_bit] ;
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end
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end
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SEL_O <= #(Tp - `Tsetup) input_data`WRITE_SEL ;
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SEL_O <= #(Tp - `Tsetup) input_data`WRITE_SEL ;
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TAG_O <= #(Tp - `Tsetup) input_data`WRITE_TAG_STIM ;
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TAG_O <= #(Tp - `Tsetup) input_data`WRITE_TAG_STIM ;
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STB_O <= #(Tp - `Tsetup) 1'b1 ;
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STB_O <= #(Tp - `Tsetup) 1'b1 ;
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