| Line 36... |
Line 36... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2003/06/12 02:30:39 mihad
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// Update!
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//
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// Revision 1.1 2002/02/01 13:39:43 mihad
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// Revision 1.1 2002/02/01 13:39:43 mihad
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// Initial testbench import. Still under development
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// Initial testbench import. Still under development
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//
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//
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`include "pci_testbench_defines.v"
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`include "pci_testbench_defines.v"
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| Line 115... |
Line 118... |
reg cab ;
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reg cab ;
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reg ok ;
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reg ok ;
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integer cyc_count ;
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integer cyc_count ;
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integer rty_count ;
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integer rty_count ;
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reg retry ;
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reg retry ;
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reg [2:0] use_cti ;
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reg [1:0] use_bte ;
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begin:main
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begin:main
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return`TB_ERROR_BIT = 1'b0 ;
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return`TB_ERROR_BIT = 1'b0 ;
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cab = 0 ;
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cab = 0 ;
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return`CYC_ACTUAL_TRANSFER = 0 ;
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return`CYC_ACTUAL_TRANSFER = 0 ;
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| Line 134... |
Line 139... |
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in_use = 1 ;
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in_use = 1 ;
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retry = 1 ;
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retry = 1 ;
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use_cti = {$random} % 8 ;
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if (use_cti === 3'b010)
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use_cti = 3'b111 ;
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else if (use_cti === 3'b001)
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use_cti = 3'b000 ;
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use_bte = {$random} % 4 ;
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write_data`WRITE_TAG_STIM = {use_cti, use_bte} ;
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while (retry === 1)
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while (retry === 1)
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begin
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begin
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// synchronize operation to clock
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// synchronize operation to clock
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if (write_flags`WB_FAST_B2B !== 1'b1)
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if (write_flags`WB_FAST_B2B !== 1'b1)
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@(posedge CLK_I) ;
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@(posedge CLK_I) ;
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| Line 207... |
Line 222... |
reg cab ;
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reg cab ;
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reg ok ;
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reg ok ;
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integer cyc_count ;
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integer cyc_count ;
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integer rty_count ;
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integer rty_count ;
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reg retry ;
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reg retry ;
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reg [2:0] use_cti ;
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reg [1:0] use_bte ;
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begin:main
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begin:main
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return`TB_ERROR_BIT = 1'b0 ;
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return`TB_ERROR_BIT = 1'b0 ;
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cab = 0 ;
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cab = 0 ;
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rty_count = 0 ;
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rty_count = 0 ;
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| Line 226... |
Line 243... |
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in_use = 1 ;
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in_use = 1 ;
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retry = 1 ;
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retry = 1 ;
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use_cti = {$random} % 8 ;
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if (use_cti === 3'b010)
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use_cti = 3'b111 ;
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else if (use_cti === 3'b001)
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use_cti = 3'b000 ;
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use_bte = {$random} % 4 ;
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read_data`READ_TAG_STIM = {use_cti, use_bte} ;
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while (retry === 1)
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while (retry === 1)
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begin
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begin
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// synchronize operation to clock
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// synchronize operation to clock
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if (read_flags`WB_FAST_B2B !== 1'b1)
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if (read_flags`WB_FAST_B2B !== 1'b1)
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@(posedge CLK_I) ;
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@(posedge CLK_I) ;
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| Line 301... |
Line 328... |
reg cab ;
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reg cab ;
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reg ok ;
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reg ok ;
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integer cyc_count ;
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integer cyc_count ;
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integer rty_count ;
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integer rty_count ;
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reg retry ;
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reg retry ;
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reg [2:0] use_cti ;
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reg [1:0] use_bte ;
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begin:main
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begin:main
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return`TB_ERROR_BIT = 1'b0 ;
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return`TB_ERROR_BIT = 1'b0 ;
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cab = 0 ;
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cab = 0 ;
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rty_count = 0 ;
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rty_count = 0 ;
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| Line 320... |
Line 349... |
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in_use = 1 ;
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in_use = 1 ;
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retry = 1 ;
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retry = 1 ;
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use_cti = {$random} % 8 ;
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if (use_cti === 3'b010)
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use_cti = 3'b111 ;
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else if (use_cti === 3'b001)
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use_cti = 3'b000 ;
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use_bte = {$random} % 4 ;
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read_data`READ_TAG_STIM = {use_cti, use_bte} ;
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while (retry === 1)
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while (retry === 1)
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begin
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begin
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// synchronize operation to clock
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// synchronize operation to clock
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if (read_flags`WB_FAST_B2B !== 1'b1)
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if (read_flags`WB_FAST_B2B !== 1'b1)
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@(posedge CLK_I) ;
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@(posedge CLK_I) ;
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| Line 398... |
Line 437... |
reg cab ;
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reg cab ;
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reg ok ;
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reg ok ;
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integer cyc_count ;
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integer cyc_count ;
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integer rty_count ;
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integer rty_count ;
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reg retry ;
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reg retry ;
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reg [2:0] use_cti ;
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reg [1:0] use_bte ;
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begin:main
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begin:main
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return`TB_ERROR_BIT = 1'b0 ;
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return`TB_ERROR_BIT = 1'b0 ;
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cab = 0 ;
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cab = 0 ;
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return`CYC_ACTUAL_TRANSFER = 0 ;
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return`CYC_ACTUAL_TRANSFER = 0 ;
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| Line 417... |
Line 458... |
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in_use = 1 ;
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in_use = 1 ;
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retry = 1 ;
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retry = 1 ;
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use_cti = {$random} % 8 ;
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if (use_cti === 3'b010)
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use_cti = 3'b111 ;
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else if (use_cti === 3'b001)
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use_cti = 3'b000 ;
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use_bte = {$random} % 4 ;
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write_data`WRITE_TAG_STIM = {use_cti, use_bte} ;
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while (retry === 1)
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while (retry === 1)
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begin
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begin
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// synchronize operation to clock
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// synchronize operation to clock
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if (write_flags`WB_FAST_B2B !== 1'b1)
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if (write_flags`WB_FAST_B2B !== 1'b1)
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@(posedge CLK_I) ;
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@(posedge CLK_I) ;
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| Line 494... |
Line 545... |
reg cab ;
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reg cab ;
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reg ok ;
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reg ok ;
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integer cyc_count ;
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integer cyc_count ;
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integer rty_count ;
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integer rty_count ;
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reg end_blk ;
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reg end_blk ;
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reg [2:0] use_cti ;
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reg [1:0] use_bte ;
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begin:main
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begin:main
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return`CYC_ACTUAL_TRANSFER = 0 ;
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return`CYC_ACTUAL_TRANSFER = 0 ;
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rty_count = 0 ;
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rty_count = 0 ;
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| Line 519... |
Line 572... |
in_use = 1 ;
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in_use = 1 ;
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if (write_flags`WB_FAST_B2B !== 1'b1)
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if (write_flags`WB_FAST_B2B !== 1'b1)
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@(posedge CLK_I) ;
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@(posedge CLK_I) ;
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cab = write_flags`WB_TRANSFER_CAB ;
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cab = write_flags`WB_TRANSFER_CAB ;
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current_write = blk_write_data[0] ;
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if (cab)
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begin:select_burst_type_blk
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reg [31:0] burst_start_adr ;
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use_cti = 3'b010 ;
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burst_start_adr = current_write`WRITE_ADDRESS ;
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if (burst_start_adr[5:2] === 4'b0000)
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use_bte = {$random} % 4 ;
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else if (burst_start_adr[4:2] === 3'b000)
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use_bte = {$random} % 3 ;
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else if (burst_start_adr[3:2] === 2'b00)
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use_bte = {$random} % 2 ;
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else
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use_bte = 2'b00 ;
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end
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else
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begin
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if ( (current_write`WRITE_TAG_STIM === 0) | (current_write`WRITE_TAG_STIM === {`WB_TAG_WIDTH{1'bx}}) )
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begin
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use_cti = {$random} % 8 ;
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if (use_cti === 3'b010)
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use_cti = 3'b111 ;
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else if (use_cti === 3'b001)
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use_cti = 3'b000 ;
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use_bte = {$random} % 4 ;
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end
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else
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begin
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{use_cti, use_bte} = current_write`WRITE_TAG_STIM ;
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end
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end
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wbm_low_level.start_cycle(cab, 1'b1, write_flags`WB_FAST_B2B, ok) ;
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wbm_low_level.start_cycle(cab, 1'b1, write_flags`WB_FAST_B2B, ok) ;
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if ( ok !== 1 )
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if ( ok !== 1 )
|
begin
|
begin
|
$display("*E, Failed to initialize cycle! Routine wb_block_write, Time %t ", $time) ;
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$display("*E, Failed to initialize cycle! Routine wb_block_write, Time %t ", $time) ;
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return`TB_ERROR_BIT = 1'b1 ;
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return`TB_ERROR_BIT = 1'b1 ;
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| Line 538... |
Line 628... |
end
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end
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end_blk = 0 ;
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end_blk = 0 ;
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while (end_blk === 0)
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while (end_blk === 0)
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begin
|
begin
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// collect data for current data beat
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// collect data for current data beat
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current_write = blk_write_data[return`CYC_ACTUAL_TRANSFER] ;
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current_write = blk_write_data[return`CYC_ACTUAL_TRANSFER] ;
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if (cab)
|
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begin
|
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if ((return`CYC_ACTUAL_TRANSFER + 1'b1) >= write_flags`WB_TRANSFER_SIZE)
|
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use_cti = 3'b111 ;
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|
end
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|
|
current_write`WRITE_TAG_STIM = {use_cti, use_bte} ;
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wbm_low_level.wbm_write(current_write, return) ;
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wbm_low_level.wbm_write(current_write, return) ;
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// check result of write operation
|
// check result of write operation
|
// check for severe test error
|
// check for severe test error
|
if (return`TB_ERROR_BIT !== 0)
|
if (return`TB_ERROR_BIT !== 0)
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| Line 578... |
Line 678... |
$display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_block_write, Time %t ", $time) ;
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$display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_block_write, Time %t ", $time) ;
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end_blk = 1 ;
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end_blk = 1 ;
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end
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end
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else
|
else
|
begin
|
begin
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if (cab)
|
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begin
|
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use_bte = 2'b00 ;
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end
|
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rty_count = rty_count + 1 ;
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rty_count = rty_count + 1 ;
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end
|
end
|
end
|
end
|
else
|
else
|
rty_count = 0 ;
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rty_count = 0 ;
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| Line 637... |
Line 742... |
reg ok ;
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reg ok ;
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integer cyc_count ;
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integer cyc_count ;
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integer rty_count ;
|
integer rty_count ;
|
reg end_blk ;
|
reg end_blk ;
|
integer transfered ;
|
integer transfered ;
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reg [2:0] use_cti ;
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reg [1:0] use_bte ;
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begin:main
|
begin:main
|
|
|
return`CYC_ACTUAL_TRANSFER = 0 ;
|
return`CYC_ACTUAL_TRANSFER = 0 ;
|
transfered = 0 ;
|
transfered = 0 ;
|
rty_count = 0 ;
|
rty_count = 0 ;
|
| Line 662... |
Line 769... |
|
|
in_use = 1 ;
|
in_use = 1 ;
|
@(posedge CLK_I) ;
|
@(posedge CLK_I) ;
|
cab = read_flags`WB_TRANSFER_CAB ;
|
cab = read_flags`WB_TRANSFER_CAB ;
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|
|
|
if (cab)
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begin:select_burst_type_blk
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reg [31:0] burst_start_adr ;
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|
|
use_cti = 3'b010 ;
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|
|
current_read = blk_read_data_in[0] ;
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burst_start_adr = current_read`READ_ADDRESS ;
|
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if (burst_start_adr[5:2] === 4'b0000)
|
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use_bte = {$random} % 4 ;
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else if (burst_start_adr[4:2] === 3'b000)
|
|
use_bte = {$random} % 3 ;
|
|
else if (burst_start_adr[3:2] === 2'b00)
|
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use_bte = {$random} % 2 ;
|
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else
|
|
use_bte = 2'b00 ;
|
|
end
|
|
|
wbm_low_level.start_cycle(cab, 1'b0, read_flags`WB_FAST_B2B, ok) ;
|
wbm_low_level.start_cycle(cab, 1'b0, read_flags`WB_FAST_B2B, ok) ;
|
|
|
if ( ok !== 1 )
|
if ( ok !== 1 )
|
begin
|
begin
|
$display("*E, Failed to initialize cycle! Routine wb_block_read, Time %t ", $time) ;
|
$display("*E, Failed to initialize cycle! Routine wb_block_read, Time %t ", $time) ;
|
| Line 685... |
Line 810... |
while (end_blk === 0)
|
while (end_blk === 0)
|
begin
|
begin
|
// collect data for current data beat
|
// collect data for current data beat
|
current_read = blk_read_data_in[return`CYC_ACTUAL_TRANSFER] ;
|
current_read = blk_read_data_in[return`CYC_ACTUAL_TRANSFER] ;
|
|
|
|
if (cab)
|
|
begin
|
|
if ((return`CYC_ACTUAL_TRANSFER + 1'b1) >= read_flags`WB_TRANSFER_SIZE)
|
|
use_cti = 3'b111 ;
|
|
end
|
|
|
|
current_read`READ_TAG_STIM = {use_cti, use_bte} ;
|
|
|
wbm_low_level.wbm_read(current_read, return) ;
|
wbm_low_level.wbm_read(current_read, return) ;
|
|
|
if ( transfered !== return`CYC_ACTUAL_TRANSFER )
|
if ( transfered !== return`CYC_ACTUAL_TRANSFER )
|
begin
|
begin
|
blk_read_data_out[transfered] = return ;
|
blk_read_data_out[transfered] = return ;
|
| Line 729... |
Line 862... |
$display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_block_read, Time %t ", $time) ;
|
$display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_block_read, Time %t ", $time) ;
|
end_blk = 1 ;
|
end_blk = 1 ;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
|
if (cab)
|
|
begin
|
|
use_bte = 2'b00 ;
|
|
end
|
|
|
rty_count = rty_count + 1 ;
|
rty_count = rty_count + 1 ;
|
end
|
end
|
end
|
end
|
else
|
else
|
rty_count = 0 ;
|
rty_count = 0 ;
|
