| Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2003/06/12 02:30:39 mihad
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// Update!
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//
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// Revision 1.3 2002/10/11 10:08:58 mihad
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// Revision 1.3 2002/10/11 10:08:58 mihad
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// Added additional testcase and changed rst name in BIST to trst
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// Added additional testcase and changed rst name in BIST to trst
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//
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//
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// Revision 1.2 2002/03/06 09:10:56 mihad
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// Revision 1.2 2002/03/06 09:10:56 mihad
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// Added missing include statements
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// Added missing include statements
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| Line 117... |
Line 120... |
wait_cyc <= 4'b0; // no wait cycles
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wait_cyc <= 4'b0; // no wait cycles
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max_retry <= 8'h0; // no retries
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max_retry <= 8'h0; // no retries
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end
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end
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end //reset
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end //reset
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reg retry_expired;
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task cycle_response;
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task cycle_response;
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input [2:0] ack_err_rty_resp; // acknowledge, error or retry response input flags
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input [2:0] ack_err_rty_resp; // acknowledge, error or retry response input flags
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input [3:0] wait_cycles; // if wait cycles before each data termination cycle (ack, err or rty)
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input [3:0] wait_cycles; // if wait cycles before each data termination cycle (ack, err or rty)
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input [7:0] retry_cycles; // noumber of retry cycles before acknowledge cycle
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input [7:0] retry_cycles; // noumber of retry cycles before acknowledge cycle
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begin
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begin
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// assign values
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// assign values
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a_e_r_resp <= #1 ack_err_rty_resp;
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a_e_r_resp <= #1 ack_err_rty_resp;
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wait_cyc <= #1 wait_cycles;
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wait_cyc <= #1 wait_cycles;
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max_retry <= #1 retry_cycles;
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max_retry <= #1 retry_cycles;
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retry_expired <= #1 0 ;
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end
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end
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endtask // cycle_response
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endtask // cycle_response
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/*------------------------------------------------------------------------------------------------------
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/*------------------------------------------------------------------------------------------------------
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Tasks for writing and reading to and from memory !!!
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Tasks for writing and reading to and from memory !!!
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| Line 206... |
Line 211... |
reg calc_err;
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reg calc_err;
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reg calc_rty;
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reg calc_rty;
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reg [7:0] retry_cnt;
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reg [7:0] retry_cnt;
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reg [7:0] retry_num;
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reg [7:0] retry_num;
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reg retry_expired;
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// Retry counter
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// Retry counter
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always@(posedge RST_I or posedge CLK_I)
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always@(posedge RST_I or posedge CLK_I)
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begin
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begin
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if (RST_I)
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if (RST_I)
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