| Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2002/03/06 09:10:56 mihad
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// Added missing include statements
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//
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// Revision 1.1 2002/02/01 13:39:43 mihad
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// Revision 1.1 2002/02/01 13:39:43 mihad
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// Initial testbench import. Still under development
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// Initial testbench import. Still under development
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//
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//
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//
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//
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`include "pci_testbench_defines.v"
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`include "pci_testbench_defines.v"
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`include "timescale.v"
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`include "timescale.v"
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`include "pci_constants.v"
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`include "pci_constants.v"
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|
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module WB_SLAVE_BEHAVIORAL
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module WB_SLAVE_BEHAVIORAL
|
(
|
(
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CLK_I,
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CLK_I,
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RST_I,
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RST_I,
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ACK_O,
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ACK_O,
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| Line 65... |
Line 69... |
STB_I,
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STB_I,
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WE_I,
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WE_I,
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CAB_I
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CAB_I
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);
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);
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/*----------------------------------------------------------------------------------------------------------------------
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/*------------------------------------------------------------------------------------------------------
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WISHBONE signals
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WISHBONE signals
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----------------------------------------------------------------------------------------------------------------------*/
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------------------------------------------------------------------------------------------------------*/
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input CLK_I ;
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input CLK_I ;
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input RST_I ;
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input RST_I ;
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output ACK_O ;
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output ACK_O ;
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input `WB_ADDR_TYPE ADR_I ;
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input `WB_ADDR_TYPE ADR_I ;
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input CYC_I ;
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input CYC_I ;
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| Line 82... |
Line 86... |
input `WB_SEL_TYPE SEL_I ;
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input `WB_SEL_TYPE SEL_I ;
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input STB_I ;
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input STB_I ;
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input WE_I ;
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input WE_I ;
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input CAB_I ;
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input CAB_I ;
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|
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//reg ACK_O ;
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reg `WB_DATA_TYPE DAT_O;
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//reg ERR_O ;
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//reg RTY_O ;
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reg [31:0] DAT_O ;
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/*----------------------------------------------------------------------------------------------------------------------
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/*------------------------------------------------------------------------------------------------------
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Asynchronous dual-port RAM signals for storing and fetching the data
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Asynchronous dual-port RAM signals for storing and fetching the data
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----------------------------------------------------------------------------------------------------------------------*/
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------------------------------------------------------------------------------------------------------*/
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reg [31:0] wb_memory [0:1023] ; // data for WB memory - 16 LSB addresses are connected
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//reg `WB_DATA_TYPE wb_memory [0:16777215]; // WB memory - 24 addresses connected - 2 LSB not used
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reg [31:0] mem_wr_data_out ;
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reg `WB_DATA_TYPE wb_memory [0:1048575]; // WB memory - 20 addresses connected - 2 LSB not used
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reg [31:0] mem_rd_data_in ;
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reg `WB_DATA_TYPE mem_wr_data_out;
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reg `WB_DATA_TYPE mem_rd_data_in;
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/*----------------------------------------------------------------------------------------------------------------------
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/*------------------------------------------------------------------------------------------------------
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Maximum values for WAIT and RETRY counters and which response !!!
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Maximum values for WAIT and RETRY counters and which response !!!
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----------------------------------------------------------------------------------------------------------------------*/
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------------------------------------------------------------------------------------------------------*/
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reg [2:0] a_e_r_resp ; // tells with which cycle_termination_signal must wb_slave respond !
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reg [2:0] a_e_r_resp ; // tells with which cycle_termination_signal must wb_slave respond !
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reg wait_cyc ;
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reg [3:0] wait_cyc;
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reg [7:0] max_retry ;
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reg [7:0] max_retry ;
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// assign registers to default state while in reset
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// assign registers to default state while in reset
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always@(RST_I)
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always@(RST_I)
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begin
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begin
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if (RST_I)
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if (RST_I)
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begin
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begin
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a_e_r_resp <= 3'b000 ; // do not respond
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a_e_r_resp <= 3'b000 ; // do not respond
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wait_cyc <= 1'b0 ; // no wait cycles
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wait_cyc <= 4'b0; // no wait cycles
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max_retry <= 8'h0 ; // no retries
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max_retry <= 8'h0 ; // no retries
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end
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end
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end //reset
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end //reset
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task cycle_response ;
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task cycle_response ;
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input [2:0] ack_err_rty_resp ; // acknowledge, error or retry response input flags
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input [2:0] ack_err_rty_resp ; // acknowledge, error or retry response input flags
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input wait_cycles ; // if wait cycles before each data termination cycle (ack, err or rty)
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input [3:0] wait_cycles; // if wait cycles before each data termination cycle (ack, err or rty)
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input [7:0] retry_cycles ; // noumber of retry cycles before acknowledge cycle
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input [7:0] retry_cycles ; // noumber of retry cycles before acknowledge cycle
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begin
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begin
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// assign values
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// assign values
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a_e_r_resp <= #1 ack_err_rty_resp ;
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a_e_r_resp <= #1 ack_err_rty_resp ;
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wait_cyc <= #1 wait_cycles ;
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wait_cyc <= #1 wait_cycles ;
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max_retry <= #1 retry_cycles ;
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max_retry <= #1 retry_cycles ;
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end
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end
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endtask // cycle_response
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endtask // cycle_response
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/*----------------------------------------------------------------------------------------------------------------------
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/*------------------------------------------------------------------------------------------------------
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|
Tasks for writing and reading to and from memory !!!
|
|
------------------------------------------------------------------------------------------------------*/
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reg `WB_ADDR_TYPE task_wr_adr_i;
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reg `WB_ADDR_TYPE task_rd_adr_i;
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reg `WB_DATA_TYPE task_dat_i;
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reg `WB_DATA_TYPE task_dat_o;
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reg `WB_SEL_TYPE task_sel_i;
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reg task_wr_data;
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reg task_data_written;
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reg `WB_DATA_TYPE task_mem_wr_data;
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// write to memory
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task wr_mem;
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input `WB_ADDR_TYPE adr_i;
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input `WB_DATA_TYPE dat_i;
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input `WB_SEL_TYPE sel_i;
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integer current_byte ;
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integer current_bit ;
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begin
|
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/*
|
|
task_data_written = 0;
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task_wr_adr_i = adr_i;
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task_dat_i = dat_i;
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task_sel_i = sel_i;
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task_wr_data = 1;
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wait(task_data_written);
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task_wr_data = 0;
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*/
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task_mem_wr_data = wb_memory[adr_i[21:2]];
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for (current_byte = 0 ; current_byte < `WB_DATA_WIDTH / 8 ; current_byte = current_byte + 1'b1)
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begin
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// check sel_i for every byte
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if (sel_i[current_byte])
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begin
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// have to write a bit at a time, because dynamic range bouds are not allowed
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for (current_bit = 0 ; current_bit < 8 ; current_bit = current_bit + 1'b1)
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task_mem_wr_data[current_byte * 8 + current_bit] = dat_i[current_byte * 8 + current_bit] ;
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end
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end
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/*if (sel_i[3])
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task_mem_wr_data[31:24] = dat_i[31:24];
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if (sel_i[2])
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task_mem_wr_data[23:16] = dat_i[23:16];
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if (sel_i[1])
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task_mem_wr_data[15: 8] = dat_i[15: 8];
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if (sel_i[0])
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task_mem_wr_data[ 7: 0] = dat_i[ 7: 0];
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*/
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wb_memory[adr_i[21:2]] = task_mem_wr_data; // write data
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end
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endtask
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// read from memory
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task rd_mem;
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input `WB_ADDR_TYPE adr_i;
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output `WB_DATA_TYPE dat_o;
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input `WB_SEL_TYPE sel_i;
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|
begin
|
|
task_rd_adr_i = adr_i;
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task_sel_i = sel_i;
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#1;
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dat_o = task_dat_o;
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end
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endtask
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/*------------------------------------------------------------------------------------------------------
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Internal signals and logic
|
Internal signals and logic
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----------------------------------------------------------------------------------------------------------------------*/
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------------------------------------------------------------------------------------------------------*/
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reg calc_ack ;
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reg calc_ack ;
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reg calc_err ;
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reg calc_err ;
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reg calc_rty ;
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reg calc_rty ;
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reg [7:0] retry_cnt ;
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reg [7:0] retry_cnt ;
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reg [7:0] retry_num ;
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reg [7:0] retry_num ;
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reg retry_expired ;
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reg retry_expired ;
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reg retry_rst ;
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// RESET retry counter
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// Retry counter
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always@(posedge RST_I or posedge CLK_I)
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always@(posedge RST_I or posedge CLK_I)
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begin
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begin
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if (RST_I)
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if (RST_I)
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retry_rst <= 1'b1 ;
|
retry_cnt <= #1 8'h00;
|
else
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else
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retry_rst <= calc_ack || calc_err ;
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|
end
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// Retry counter
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always@(posedge retry_rst or negedge calc_rty)
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begin
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begin
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if (retry_rst)
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if (calc_ack || calc_err)
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retry_cnt <= #`FF_DELAY 8'h00 ;
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retry_cnt <= #1 8'h00;
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else
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else if (calc_rty)
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retry_cnt <= #`FF_DELAY retry_num ;
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retry_cnt <= #1 retry_num;
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end
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end
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end
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always@(retry_cnt or max_retry)
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always@(retry_cnt or max_retry)
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begin
|
begin
|
if (retry_cnt < max_retry)
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if (retry_cnt < max_retry)
|
begin
|
begin
|
retry_num = retry_cnt + 1'b1 ;
|
retry_num = retry_cnt + 1'b1 ;
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retry_expired = #10 1'b0 ;
|
retry_expired = 1'b0;
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end
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end
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else
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else
|
begin
|
begin
|
retry_num = retry_cnt ;
|
retry_num = retry_cnt ;
|
retry_expired = #10 1'b1 ;
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retry_expired = 1'b1;
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end
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end
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end
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end
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|
reg [1:0] wait_cnt ;
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reg [3:0] wait_cnt;
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reg [1:0] wait_num ;
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reg [3:0] wait_num;
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reg wait_expired ;
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reg wait_expired ;
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reg reset_wait ;
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// Wait counter
|
always@(posedge RST_I or posedge CLK_I)
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always@(posedge RST_I or posedge CLK_I)
|
begin
|
begin
|
if (RST_I)
|
if (RST_I)
|
reset_wait <= #`FF_DELAY 1'b1 ;
|
wait_cnt <= #1 4'h0;
|
else
|
else
|
reset_wait <= #`FF_DELAY (wait_expired || ~STB_I) ;
|
|
end
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// Wait counter
|
|
always@(posedge reset_wait or posedge CLK_I)
|
|
begin
|
begin
|
if (reset_wait)
|
if (wait_expired || ~STB_I)
|
wait_cnt <= #`FF_DELAY 4'h0 ;
|
wait_cnt <= #1 4'h0;
|
else
|
else
|
wait_cnt <= #`FF_DELAY wait_num ;
|
wait_cnt <= #1 wait_num;
|
|
end
|
end
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end
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|
always@(wait_cnt or wait_cyc or STB_I or a_e_r_resp or retry_expired)
|
always@(wait_cnt or wait_cyc or STB_I or a_e_r_resp or retry_expired)
|
begin
|
begin
|
if ((wait_cyc) && (STB_I))
|
if ((wait_cyc > 0) && (STB_I))
|
begin
|
begin
|
if (wait_cnt < 2'h2)
|
if (wait_cnt < wait_cyc) // 4'h2)
|
begin
|
begin
|
wait_num = wait_cnt + 1'b1 ;
|
wait_num = wait_cnt + 1'b1 ;
|
wait_expired = 1'b0 ;
|
wait_expired = 1'b0 ;
|
calc_ack = 1'b0 ;
|
calc_ack = 1'b0 ;
|
calc_err = 1'b0 ;
|
calc_err = 1'b0 ;
|
| Line 241... |
Line 304... |
calc_rty = 1'b0 ;
|
calc_rty = 1'b0 ;
|
end
|
end
|
end
|
end
|
end
|
end
|
else
|
else
|
if ((~wait_cyc) && (STB_I))
|
if ((wait_cyc == 0) && (STB_I))
|
begin
|
begin
|
wait_num = 2'h0 ;
|
wait_num = 2'h0 ;
|
wait_expired = 1'b1 ;
|
wait_expired = 1'b1 ;
|
if (a_e_r_resp == 3'b100)
|
if (a_e_r_resp == 3'b100)
|
begin
|
begin
|
calc_ack = 1'b1 ;
|
calc_ack = 1'b1 ;
|
calc_err = 1'b0 ;
|
calc_err = 1'b0 ;
|
calc_rty = 1'b0 ;
|
calc_rty = 1'b0 ;
|
end
|
end
|
else
|
else if (a_e_r_resp == 3'b010)
|
if (a_e_r_resp == 3'b010)
|
|
begin
|
begin
|
calc_ack = 1'b0 ;
|
calc_ack = 1'b0 ;
|
calc_err = 1'b1 ;
|
calc_err = 1'b1 ;
|
calc_rty = 1'b0 ;
|
calc_rty = 1'b0 ;
|
end
|
end
|
else
|
else if (a_e_r_resp == 3'b001)
|
if (a_e_r_resp == 3'b001)
|
|
begin
|
begin
|
calc_err = 1'b0 ;
|
calc_err = 1'b0 ;
|
if (retry_expired)
|
if (retry_expired)
|
begin
|
begin
|
calc_ack = 1'b1 ;
|
calc_ack = 1'b1 ;
|
| Line 294... |
Line 355... |
|
|
wire rd_sel = (CYC_I && STB_I && ~WE_I) ;
|
wire rd_sel = (CYC_I && STB_I && ~WE_I) ;
|
wire wr_sel = (CYC_I && STB_I && WE_I) ;
|
wire wr_sel = (CYC_I && STB_I && WE_I) ;
|
|
|
// Generate cycle termination signals
|
// Generate cycle termination signals
|
assign ACK_O = calc_ack && STB_I ;
|
assign ACK_O = calc_ack && STB_I && CYC_I;
|
assign ERR_O = calc_err && STB_I ;
|
assign ERR_O = calc_err && STB_I && CYC_I;
|
assign RTY_O = calc_rty && STB_I ;
|
assign RTY_O = calc_rty && STB_I && CYC_I;
|
|
|
// Assign address to asynchronous memory
|
// Assign address to asynchronous memory
|
always@(ADR_I or RST_I)
|
always@(RST_I or ADR_I)
|
begin
|
begin
|
if (RST_I) // this is added because at start of test bench we need address change in order to get data!
|
if (RST_I) // this is added because at start of test bench we need address change in order to get data!
|
mem_rd_data_in = 32'hxxxx_xxxx ;
|
begin
|
|
#1 mem_rd_data_in = `WB_DATA_WIDTH'hxxxx_xxxx;
|
|
end
|
else
|
else
|
mem_rd_data_in = wb_memory[ADR_I[11:2]] ;
|
begin
|
|
// #1 mem_rd_data_in = wb_memory[ADR_I[25:2]];
|
|
#1 mem_rd_data_in = wb_memory[ADR_I[21:2]];
|
|
end
|
end
|
end
|
|
|
// assign outputs to unknown state while in reset
|
/*// Data input/output interface
|
always@(RST_I)
|
always@(rd_sel or mem_rd_data_in or RST_I)
|
begin
|
begin
|
if (RST_I)
|
if (RST_I)
|
|
DAT_O <=#1 `WB_DATA_WIDTH'hxxxx_xxxx; // assign outputs to unknown state while in reset
|
|
else if (rd_sel)
|
|
DAT_O <=#1 mem_rd_data_in;
|
|
else
|
|
DAT_O <=#1 `WB_DATA_WIDTH'hxxxx_xxxx;
|
|
end
|
|
*/
|
|
always@
|
|
(
|
|
RST_I or
|
|
ACK_O or
|
|
WE_I or
|
|
ADR_I
|
|
)
|
begin
|
begin
|
DAT_O <= 32'hxxxx_xxxx ;
|
if ((ACK_O === 1'b1) && (RST_I === 1'b0) && (WE_I === 1'b0))
|
|
DAT_O <= #1 wb_memory[ADR_I[21:2]] ;
|
|
else
|
|
DAT_O <= #1 {`WB_DATA_WIDTH{1'bx}} ;
|
end
|
end
|
end //reset
|
|
|
|
// Data input/output interface
|
always@(RST_I or task_rd_adr_i)
|
always@(rd_sel or wr_sel or mem_rd_data_in or DAT_I or SEL_I or mem_wr_data_out)
|
|
begin
|
begin
|
if (rd_sel)
|
if (RST_I)
|
begin
|
task_dat_o = `WB_DATA_WIDTH'hxxxx_xxxx;
|
DAT_O = mem_rd_data_in ;
|
else
|
end
|
task_dat_o = wb_memory[task_rd_adr_i[21:2]];
|
end
|
end
|
|
|
|
/*always@(CLK_I or wr_sel or task_wr_data or ADR_I or task_wr_adr_i or
|
|
mem_wr_data_out or DAT_I or task_dat_i or
|
|
SEL_I or task_sel_i)
|
|
begin
|
|
if (task_wr_data)
|
|
begin
|
|
task_mem_wr_data = wb_memory[task_wr_adr_i[21:2]];
|
|
|
|
if (task_sel_i[3])
|
|
task_mem_wr_data[31:24] = task_dat_i[31:24];
|
|
if (task_sel_i[2])
|
|
task_mem_wr_data[23:16] = task_dat_i[23:16];
|
|
if (task_sel_i[1])
|
|
task_mem_wr_data[15: 8] = task_dat_i[15: 8];
|
|
if (task_sel_i[0])
|
|
task_mem_wr_data[ 7: 0] = task_dat_i[ 7: 0];
|
|
|
|
wb_memory[task_wr_adr_i[21:2]] = task_mem_wr_data; // write data
|
|
task_data_written = 1;
|
|
end
|
|
else if (wr_sel && CLK_I)
|
|
begin
|
|
// mem_wr_data_out = wb_memory[ADR_I[25:2]]; // if no SEL_I is active, old value will be written
|
|
mem_wr_data_out = wb_memory[ADR_I[21:2]]; // if no SEL_I is active, old value will be written
|
|
|
|
if (SEL_I[3])
|
|
mem_wr_data_out[31:24] = DAT_I[31:24];
|
|
if (SEL_I[2])
|
|
mem_wr_data_out[23:16] = DAT_I[23:16];
|
|
if (SEL_I[1])
|
|
mem_wr_data_out[15: 8] = DAT_I[15: 8];
|
|
if (SEL_I[0])
|
|
mem_wr_data_out[ 7: 0] = DAT_I[ 7: 0];
|
|
|
|
// wb_memory[ADR_I[25:2]] <= mem_wr_data_out; // write data
|
|
wb_memory[ADR_I[21:2]] = mem_wr_data_out; // write data
|
|
end
|
|
end
|
|
*/
|
always@(posedge CLK_I)
|
always@(posedge CLK_I)
|
begin
|
begin
|
if (wr_sel)
|
if (CYC_I && STB_I && WE_I && ACK_O)
|
begin
|
wr_mem(ADR_I, DAT_I, SEL_I) ;
|
mem_wr_data_out = wb_memory[ADR_I[11:2]] ;
|
|
|
|
if ( SEL_I[3] )
|
|
mem_wr_data_out[31:24] = DAT_I[31:24] ;
|
|
|
|
if ( SEL_I[2] )
|
|
mem_wr_data_out[23:16] = DAT_I[23:16] ;
|
|
|
|
if ( SEL_I[1] )
|
|
mem_wr_data_out[15: 8] = DAT_I[15: 8] ;
|
|
|
|
if ( SEL_I[0] )
|
|
mem_wr_data_out[ 7: 0] = DAT_I[ 7: 0] ;
|
|
|
|
wb_memory[ADR_I[11:2]] <= mem_wr_data_out ;
|
|
end
|
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
