| Line 41... |
Line 41... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2001/10/05 08:14:28 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
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// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
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// New project directory structure
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// New project directory structure
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//
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//
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//
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//
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`include "constants.v"
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`include "pci_constants.v"
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// this is top level module of pci bridge core
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// this is top level module of pci bridge core
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// it instantiates and connects other lower level modules
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// it instantiates and connects other lower level modules
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// check polarity of PCI output enables in file out_reg.v and change it according to IO interface specification
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// check polarity of PCI output enables in file out_reg.v and change it according to IO interface specification
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| Line 247... |
Line 253... |
output PCI_SERRn_EN_OUT ;
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output PCI_SERRn_EN_OUT ;
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// declare clock and reset wires
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// declare clock and reset wires
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wire pci_clk = PCI_CLK_IN ;
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wire pci_clk = PCI_CLK_IN ;
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wire wb_clk = CLK_I ;
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wire wb_clk = CLK_I ;
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wire reset ; // assigned at pci bridge reset and interrupt logic
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assign PCI_RSTn_OUT = 1'b0 ;
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/*=========================================================================================================
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First comes definition of all modules' outputs, so they can be assigned to any other module's input later
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`ifdef HOST
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in the file, when module is instantiated
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// host implementation of the bridge gets its reset from WISHBONE bus - RST_I and propagates it to PCI bus
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=========================================================================================================*/
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wire reset = RST_I ;
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// PCI BRIDGE RESET AND INTERRUPT LOGIC OUTPUTS
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assign PCI_RSTn_EN_OUT = ~reset ;
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wire pci_reso_reset ;
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assign RST_O = 1'b0 ;
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wire pci_reso_pci_rstn_out ;
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`else
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wire pci_reso_pci_rstn_en_out ;
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`ifdef GUEST
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wire pci_reso_rst_o ;
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// guest implementation of the bridge gets its reset from PCI bus - RST# and propagates it to WISHBONE bus
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wire pci_into_pci_intan_out ;
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wire reset = ~PCI_RSTn_IN ;
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wire pci_into_pci_intan_en_out ;
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assign RST_O = reset ;
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wire pci_into_int_o ;
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assign PCI_RSTn_EN_OUT = 1'b1 ;
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wire pci_into_conf_isr_int_prop_out ;
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`endif
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`endif
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// assign pci bridge reset interrupt logic outputs to top outputs where possible
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assign reset = pci_reso_reset ;
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assign PCI_RSTn_OUT = pci_reso_pci_rstn_out ;
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assign PCI_RSTn_EN_OUT = pci_reso_pci_rstn_en_out ;
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assign RST_O = pci_reso_rst_o ;
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assign PCI_INTAn_OUT = pci_into_pci_intan_out ;
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assign PCI_INTAn_EN_OUT = pci_into_pci_intan_en_out ;
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assign INT_O = pci_into_int_o ;
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/*==================================================================================================================================================
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Interrupts not yet implemented
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==================================================================================================================================================*/
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assign INT_O = 1'b0 ;
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assign PCI_INTAn_EN_OUT = 1'b1 ;
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assign PCI_INTAn_OUT = 1'b1 ;
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/*==================================================================================================================================================
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First comes definition of all modules' outputs, so they can be assigned to any other module's input later in the file, when module is instantiated
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==================================================================================================================================================*/
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// WISHBONE SLAVE UNIT OUTPUTS
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// WISHBONE SLAVE UNIT OUTPUTS
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wire [31:0] wbu_sdata_out ;
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wire [31:0] wbu_sdata_out ;
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wire wbu_ack_out ;
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wire wbu_ack_out ;
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wire wbu_rty_out ;
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wire wbu_rty_out ;
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wire wbu_err_out ;
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wire wbu_err_out ;
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| Line 302... |
Line 306... |
wire wbu_conf_wenable_out ;
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wire wbu_conf_wenable_out ;
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wire [3:0] wbu_conf_be_out ;
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wire [3:0] wbu_conf_be_out ;
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wire [31:0] wbu_conf_data_out ;
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wire [31:0] wbu_conf_data_out ;
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wire wbu_del_read_comp_pending_out ;
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wire wbu_del_read_comp_pending_out ;
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wire wbu_wbw_fifo_empty_out ;
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wire wbu_wbw_fifo_empty_out ;
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wire wbu_pciif_load_next_out ;
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wire wbu_ad_load_out ;
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wire wbu_ad_load_on_transfer_out ;
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wire wbu_pciif_frame_load_out ;
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wire wbu_pciif_frame_load_out ;
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// assign wishbone slave unit's outputs to top outputs where possible
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// assign wishbone slave unit's outputs to top outputs where possible
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assign SDAT_O = wbu_sdata_out ;
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assign SDAT_O = wbu_sdata_out ;
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assign ACK_O = wbu_ack_out ;
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assign ACK_O = wbu_ack_out ;
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| Line 325... |
Line 330... |
wire pciu_pciif_stop_out ;
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wire pciu_pciif_stop_out ;
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wire pciu_pciif_devsel_out ;
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wire pciu_pciif_devsel_out ;
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wire pciu_pciif_trdy_en_out ;
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wire pciu_pciif_trdy_en_out ;
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wire pciu_pciif_stop_en_out ;
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wire pciu_pciif_stop_en_out ;
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wire pciu_pciif_devsel_en_out ;
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wire pciu_pciif_devsel_en_out ;
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wire pciu_pciif_target_load_out ;
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wire pciu_ad_load_out ;
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wire pciu_ad_load_on_transfer_out ;
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wire [31:0] pciu_pciif_ad_out ;
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wire [31:0] pciu_pciif_ad_out ;
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wire pciu_pciif_ad_en_out ;
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wire pciu_pciif_ad_en_out ;
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wire pciu_pciif_tabort_set_out ;
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wire pciu_pciif_tabort_set_out ;
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wire [31:0] pciu_err_addr_out ;
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wire [31:0] pciu_err_addr_out ;
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wire [3:0] pciu_err_bc_out ;
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wire [3:0] pciu_err_bc_out ;
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| Line 362... |
Line 368... |
wire conf_serr_enable_out ;
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wire conf_serr_enable_out ;
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wire conf_perr_response_out ;
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wire conf_perr_response_out ;
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wire conf_pci_master_enable_out ;
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wire conf_pci_master_enable_out ;
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wire conf_mem_space_enable_out ;
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wire conf_mem_space_enable_out ;
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wire conf_io_space_enable_out ;
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wire conf_io_space_enable_out ;
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wire [7:0] conf_cache_line_size_out ;
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wire [7:0] conf_cache_line_size_to_pci_out ;
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wire [7:0] conf_cache_line_size_to_wb_out ;
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wire conf_cache_lsize_not_zero_to_wb_out ;
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wire [7:0] conf_latency_tim_out ;
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wire [7:0] conf_latency_tim_out ;
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wire [2:0] conf_int_pin_out ;
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wire [19:0] conf_pci_ba0_out ;
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wire [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)] conf_pci_ba0_out ;
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wire [19:0] conf_pci_ba1_out ;
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wire [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)] conf_pci_ba1_out ;
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wire [19:0] conf_pci_ba2_out ;
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wire [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)] conf_pci_ba2_out ;
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wire [19:0] conf_pci_ba3_out ;
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wire [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)] conf_pci_ba3_out ;
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wire [19:0] conf_pci_ba4_out ;
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wire [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)] conf_pci_ba4_out ;
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wire [19:0] conf_pci_ba5_out ;
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wire [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)] conf_pci_ba5_out ;
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wire [19:0] conf_pci_ta0_out ;
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wire [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)] conf_pci_ta0_out ;
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wire [19:0] conf_pci_ta1_out ;
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wire [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)] conf_pci_ta1_out ;
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wire [19:0] conf_pci_ta2_out ;
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wire [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)] conf_pci_ta2_out ;
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wire [19:0] conf_pci_ta3_out ;
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wire [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)] conf_pci_ta3_out ;
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wire [19:0] conf_pci_ta4_out ;
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wire [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)] conf_pci_ta4_out ;
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wire [19:0] conf_pci_ta5_out ;
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wire [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)] conf_pci_ta5_out ;
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wire [19:0] conf_pci_am0_out ;
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wire [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)] conf_pci_am0_out ;
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wire [19:0] conf_pci_am1_out ;
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wire [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)] conf_pci_am1_out ;
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wire [19:0] conf_pci_am2_out ;
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wire [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)] conf_pci_am2_out ;
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wire [19:0] conf_pci_am3_out ;
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wire [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)] conf_pci_am3_out ;
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wire [19:0] conf_pci_am4_out ;
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wire [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)] conf_pci_am4_out ;
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wire [19:0] conf_pci_am5_out ;
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wire [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)] conf_pci_am5_out ;
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wire conf_pci_mem_io0_out ;
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wire conf_pci_mem_io0_out ;
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wire conf_pci_mem_io1_out ;
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wire conf_pci_mem_io1_out ;
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wire conf_pci_mem_io2_out ;
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wire conf_pci_mem_io2_out ;
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wire conf_pci_mem_io3_out ;
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wire conf_pci_mem_io3_out ;
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| Line 399... |
Line 406... |
wire [1:0] conf_pci_img_ctrl2_out ;
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wire [1:0] conf_pci_img_ctrl2_out ;
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wire [1:0] conf_pci_img_ctrl3_out ;
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wire [1:0] conf_pci_img_ctrl3_out ;
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wire [1:0] conf_pci_img_ctrl4_out ;
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wire [1:0] conf_pci_img_ctrl4_out ;
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wire [1:0] conf_pci_img_ctrl5_out ;
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wire [1:0] conf_pci_img_ctrl5_out ;
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wire conf_pci_err_rty_exp_out ;
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wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ba0_out ;
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wire conf_pci_error_en_out ;
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wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ba1_out ;
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wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ba2_out ;
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wire [19:0] conf_wb_ba0_out ;
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wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ba3_out ;
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wire [19:0] conf_wb_ba1_out ;
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wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ba4_out ;
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wire [19:0] conf_wb_ba2_out ;
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wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ba5_out ;
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wire [19:0] conf_wb_ba3_out ;
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wire [19:0] conf_wb_ba4_out ;
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wire [19:0] conf_wb_ba5_out ;
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wire conf_wb_mem_io0_out ;
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wire conf_wb_mem_io0_out ;
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wire conf_wb_mem_io1_out ;
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wire conf_wb_mem_io1_out ;
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wire conf_wb_mem_io2_out ;
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wire conf_wb_mem_io2_out ;
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wire conf_wb_mem_io3_out ;
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wire conf_wb_mem_io3_out ;
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wire conf_wb_mem_io4_out ;
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wire conf_wb_mem_io4_out ;
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wire conf_wb_mem_io5_out ;
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wire conf_wb_mem_io5_out ;
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wire [19:0] conf_wb_am0_out ;
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wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_am0_out ;
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wire [19:0] conf_wb_am1_out ;
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wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_am1_out ;
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wire [19:0] conf_wb_am2_out ;
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wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_am2_out ;
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wire [19:0] conf_wb_am3_out ;
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wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_am3_out ;
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wire [19:0] conf_wb_am4_out ;
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wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_am4_out ;
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wire [19:0] conf_wb_am5_out ;
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wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_am5_out ;
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wire [19:0] conf_wb_ta0_out ;
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wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ta0_out ;
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wire [19:0] conf_wb_ta1_out ;
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wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ta1_out ;
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wire [19:0] conf_wb_ta2_out ;
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wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ta2_out ;
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wire [19:0] conf_wb_ta3_out ;
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wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ta3_out ;
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wire [19:0] conf_wb_ta4_out ;
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wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ta4_out ;
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wire [19:0] conf_wb_ta5_out ;
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wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ta5_out ;
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wire [2:0] conf_wb_img_ctrl0_out ;
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wire [2:0] conf_wb_img_ctrl0_out ;
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wire [2:0] conf_wb_img_ctrl1_out ;
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wire [2:0] conf_wb_img_ctrl1_out ;
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wire [2:0] conf_wb_img_ctrl2_out ;
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wire [2:0] conf_wb_img_ctrl2_out ;
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wire [2:0] conf_wb_img_ctrl3_out ;
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wire [2:0] conf_wb_img_ctrl3_out ;
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wire [2:0] conf_wb_img_ctrl4_out ;
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wire [2:0] conf_wb_img_ctrl4_out ;
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wire [2:0] conf_wb_img_ctrl5_out ;
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wire [2:0] conf_wb_img_ctrl5_out ;
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wire conf_wb_err_rty_exp_out ;
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wire conf_wb_err_en_out ;
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wire [23:0] conf_ccyc_addr_out ;
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wire [23:0] conf_ccyc_addr_out ;
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wire conf_soft_res_out ;
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wire conf_soft_res_out ;
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wire conf_serr_int_en_out ;
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wire conf_int_out ;
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wire conf_perr_int_en_out ;
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wire conf_err_int_en_out ;
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wire conf_int_prop_en_out ;
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wire conf_pci_err_pending_out ;
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wire conf_wb_err_pending_out ;
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// PCI IO MUX OUTPUTS
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// PCI IO MUX OUTPUTS
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wire pci_mux_frame_out ;
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wire pci_mux_frame_out ;
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wire pci_mux_irdy_out ;
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wire pci_mux_irdy_out ;
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wire pci_mux_devsel_out ;
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wire pci_mux_devsel_out ;
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wire pci_mux_trdy_out ;
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wire pci_mux_trdy_out ;
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wire pci_mux_stop_out ;
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wire pci_mux_stop_out ;
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wire [3:0] pci_mux_cbe_out ;
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wire [3:0] pci_mux_cbe_out ;
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wire [31:0] pci_mux_ad_out ;
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wire [31:0] pci_mux_ad_out ;
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wire pci_mux_ad_load_out ;
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wire [31:0] pci_mux_ad_en_out ;
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wire [31:0] pci_mux_ad_en_out ;
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wire pci_mux_ad_en_unregistered_out ;
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wire pci_mux_frame_en_out ;
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wire pci_mux_frame_en_out ;
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wire pci_mux_irdy_en_out ;
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wire pci_mux_irdy_en_out ;
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wire pci_mux_devsel_en_out ;
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wire pci_mux_devsel_en_out ;
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wire pci_mux_trdy_en_out ;
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wire pci_mux_trdy_en_out ;
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wire pci_mux_stop_en_out ;
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wire pci_mux_stop_en_out ;
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| Line 547... |
Line 546... |
wire in_reg_devsel_out ;
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wire in_reg_devsel_out ;
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wire in_reg_idsel_out ;
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wire in_reg_idsel_out ;
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wire [31:0] in_reg_ad_out ;
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wire [31:0] in_reg_ad_out ;
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wire [3:0] in_reg_cbe_out ;
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wire [3:0] in_reg_cbe_out ;
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|
|
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/*=========================================================================================================
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|
Now comes definition of all modules' and their appropriate inputs
|
|
=========================================================================================================*/
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// PCI BRIDGE RESET AND INTERRUPT LOGIC INPUTS
|
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wire pci_resi_rst_i = RST_I ;
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wire pci_resi_pci_rstn_in = PCI_RSTn_IN ;
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wire pci_resi_conf_soft_res_in = conf_soft_res_out ;
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wire pci_inti_pci_intan_in = PCI_INTAn_IN ;
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wire pci_inti_conf_int_in = conf_int_out ;
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wire pci_inti_int_i = INT_I ;
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wire pci_inti_out_bckp_perr_en_in = out_bckp_perr_en_out ;
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wire pci_inti_out_bckp_serr_en_in = out_bckp_serr_en_out ;
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|
|
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PCI_RST_INT pci_resets_and_interrupts
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(
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.clk_in (pci_clk),
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.rst_i (pci_resi_rst_i),
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.pci_rstn_in (pci_resi_pci_rstn_in),
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.conf_soft_res_in (pci_resi_conf_soft_res_in),
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.reset (pci_reso_reset),
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.pci_rstn_out (pci_reso_pci_rstn_out),
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.pci_rstn_en_out (pci_reso_pci_rstn_en_out),
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.rst_o (pci_reso_rst_o),
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.pci_intan_in (pci_inti_pci_intan_in),
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.conf_int_in (pci_inti_conf_int_in),
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.int_i (pci_inti_int_i),
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.out_bckp_perr_en_in (pci_inti_out_bckp_perr_en_in),
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.out_bckp_serr_en_in (pci_inti_out_bckp_serr_en_in),
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.pci_intan_out (pci_into_pci_intan_out),
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.pci_intan_en_out (pci_into_pci_intan_en_out),
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.int_o (pci_into_int_o),
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.conf_isr_int_prop_out (pci_into_conf_isr_int_prop_out)
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);
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// WISHBONE SLAVE UNIT INPUTS
|
// WISHBONE SLAVE UNIT INPUTS
|
wire [31:0] wbu_addr_in = ADR_I ;
|
wire [31:0] wbu_addr_in = ADR_I ;
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wire [31:0] wbu_sdata_in = SDAT_I ;
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wire [31:0] wbu_sdata_in = SDAT_I ;
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wire wbu_cyc_in = CYC_I ;
|
wire wbu_cyc_in = CYC_I ;
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| Line 615... |
Line 635... |
`ifdef GUEST
|
`ifdef GUEST
|
wire [31:0] wbu_conf_data_in = conf_r_data_out ;
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wire [31:0] wbu_conf_data_in = conf_r_data_out ;
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`endif
|
`endif
|
`endif
|
`endif
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|
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wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar0_in = conf_wb_ba0_out[19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] ;
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wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar0_in = conf_wb_ba0_out ;
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wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar1_in = conf_wb_ba1_out[19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] ;
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wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar1_in = conf_wb_ba1_out ;
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wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar2_in = conf_wb_ba2_out[19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] ;
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wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar2_in = conf_wb_ba2_out ;
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wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar3_in = conf_wb_ba3_out[19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] ;
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wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar3_in = conf_wb_ba3_out ;
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wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar4_in = conf_wb_ba4_out[19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar4_in = conf_wb_ba4_out ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar5_in = conf_wb_ba5_out[19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar5_in = conf_wb_ba5_out ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am0_in = conf_wb_am0_out[19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am0_in = conf_wb_am0_out ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am1_in = conf_wb_am1_out[19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am1_in = conf_wb_am1_out ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am2_in = conf_wb_am2_out[19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am2_in = conf_wb_am2_out ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am3_in = conf_wb_am3_out[19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am3_in = conf_wb_am3_out ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am4_in = conf_wb_am4_out[19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am4_in = conf_wb_am4_out ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am5_in = conf_wb_am5_out[19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am5_in = conf_wb_am5_out ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta0_in = conf_wb_ta0_out[19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta0_in = conf_wb_ta0_out ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta1_in = conf_wb_ta1_out[19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta1_in = conf_wb_ta1_out ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta2_in = conf_wb_ta2_out[19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta2_in = conf_wb_ta2_out ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta3_in = conf_wb_ta3_out[19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta3_in = conf_wb_ta3_out ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta4_in = conf_wb_ta4_out[19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta4_in = conf_wb_ta4_out ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta5_in = conf_wb_ta5_out[19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta5_in = conf_wb_ta5_out ;
|
|
|
wire [23:0] wbu_ccyc_addr_in = conf_ccyc_addr_out ;
|
wire [23:0] wbu_ccyc_addr_in = conf_ccyc_addr_out ;
|
wire wbu_master_enable_in = conf_pci_master_enable_out ;
|
wire wbu_master_enable_in = conf_pci_master_enable_out ;
|
wire [7:0] wbu_cache_line_size_in = conf_cache_line_size_out ;
|
wire wbu_cache_line_size_not_zero = conf_cache_lsize_not_zero_to_wb_out ;
|
|
wire [7:0] wbu_cache_line_size_in = conf_cache_line_size_to_pci_out ;
|
|
|
wire wbu_pciif_gnt_in = PCI_GNTn_IN ;
|
wire wbu_pciif_gnt_in = PCI_GNTn_IN ;
|
wire wbu_pciif_frame_in = in_reg_frame_out ;
|
wire wbu_pciif_frame_in = in_reg_frame_out ;
|
wire wbu_pciif_irdy_in = in_reg_irdy_out ;
|
wire wbu_pciif_irdy_in = in_reg_irdy_out ;
|
wire wbu_pciif_trdy_in = PCI_TRDYn_IN ;
|
wire wbu_pciif_trdy_in = PCI_TRDYn_IN ;
|
| Line 650... |
Line 671... |
wire wbu_pciif_trdy_reg_in = in_reg_trdy_out ;
|
wire wbu_pciif_trdy_reg_in = in_reg_trdy_out ;
|
wire wbu_pciif_stop_reg_in = in_reg_stop_out ;
|
wire wbu_pciif_stop_reg_in = in_reg_stop_out ;
|
wire wbu_pciif_devsel_reg_in = in_reg_devsel_out ;
|
wire wbu_pciif_devsel_reg_in = in_reg_devsel_out ;
|
|
|
|
|
wire wbu_err_pending_in = conf_wb_err_pending_out ;
|
|
wire [7:0] wbu_latency_tim_val_in = conf_latency_tim_out ;
|
wire [7:0] wbu_latency_tim_val_in = conf_latency_tim_out ;
|
|
|
wire wbu_pciif_frame_en_in = out_bckp_frame_en_out ;
|
wire wbu_pciif_frame_en_in = out_bckp_frame_en_out ;
|
wire wbu_pciif_frame_out_in = out_bckp_frame_out ;
|
wire wbu_pciif_frame_out_in = out_bckp_frame_out ;
|
|
|
| Line 699... |
Line 719... |
.wbu_ta4_in (wbu_ta4_in),
|
.wbu_ta4_in (wbu_ta4_in),
|
.wbu_ta5_in (wbu_ta5_in),
|
.wbu_ta5_in (wbu_ta5_in),
|
.wbu_at_en_in (wbu_at_en_in),
|
.wbu_at_en_in (wbu_at_en_in),
|
.wbu_ccyc_addr_in (wbu_ccyc_addr_in),
|
.wbu_ccyc_addr_in (wbu_ccyc_addr_in),
|
.wbu_master_enable_in (wbu_master_enable_in),
|
.wbu_master_enable_in (wbu_master_enable_in),
|
|
.wbu_cache_line_size_not_zero (wbu_cache_line_size_not_zero),
|
.wbu_cache_line_size_in (wbu_cache_line_size_in),
|
.wbu_cache_line_size_in (wbu_cache_line_size_in),
|
.wbu_pciif_gnt_in (wbu_pciif_gnt_in),
|
.wbu_pciif_gnt_in (wbu_pciif_gnt_in),
|
.wbu_pciif_frame_in (wbu_pciif_frame_in),
|
.wbu_pciif_frame_in (wbu_pciif_frame_in),
|
.wbu_pciif_frame_en_in (wbu_pciif_frame_en_in),
|
.wbu_pciif_frame_en_in (wbu_pciif_frame_en_in),
|
.wbu_pciif_frame_out_in (wbu_pciif_frame_out_in),
|
.wbu_pciif_frame_out_in (wbu_pciif_frame_out_in),
|
| Line 724... |
Line 745... |
.wbu_err_addr_out (wbu_err_addr_out),
|
.wbu_err_addr_out (wbu_err_addr_out),
|
.wbu_err_bc_out (wbu_err_bc_out),
|
.wbu_err_bc_out (wbu_err_bc_out),
|
.wbu_err_signal_out (wbu_err_signal_out),
|
.wbu_err_signal_out (wbu_err_signal_out),
|
.wbu_err_source_out (wbu_err_source_out),
|
.wbu_err_source_out (wbu_err_source_out),
|
.wbu_err_rty_exp_out (wbu_err_rty_exp_out),
|
.wbu_err_rty_exp_out (wbu_err_rty_exp_out),
|
.wbu_err_pending_in (wbu_err_pending_in),
|
|
.wbu_tabort_rec_out (wbu_tabort_rec_out),
|
.wbu_tabort_rec_out (wbu_tabort_rec_out),
|
.wbu_mabort_rec_out (wbu_mabort_rec_out),
|
.wbu_mabort_rec_out (wbu_mabort_rec_out),
|
.wbu_conf_offset_out (wbu_conf_offset_out),
|
.wbu_conf_offset_out (wbu_conf_offset_out),
|
.wbu_conf_renable_out (wbu_conf_renable_out),
|
.wbu_conf_renable_out (wbu_conf_renable_out),
|
.wbu_conf_wenable_out (wbu_conf_wenable_out),
|
.wbu_conf_wenable_out (wbu_conf_wenable_out),
|
.wbu_conf_be_out (wbu_conf_be_out),
|
.wbu_conf_be_out (wbu_conf_be_out),
|
.wbu_conf_data_out (wbu_conf_data_out),
|
.wbu_conf_data_out (wbu_conf_data_out),
|
.wbu_del_read_comp_pending_out (wbu_del_read_comp_pending_out),
|
.wbu_del_read_comp_pending_out (wbu_del_read_comp_pending_out),
|
.wbu_wbw_fifo_empty_out (wbu_wbw_fifo_empty_out),
|
.wbu_wbw_fifo_empty_out (wbu_wbw_fifo_empty_out),
|
.wbu_latency_tim_val_in (wbu_latency_tim_val_in),
|
.wbu_latency_tim_val_in (wbu_latency_tim_val_in),
|
.wbu_pciif_load_next_out (wbu_pciif_load_next_out),
|
.wbu_ad_load_out (wbu_ad_load_out),
|
|
.wbu_ad_load_on_transfer_out (wbu_ad_load_on_transfer_out),
|
.wbu_pciif_trdy_reg_in (wbu_pciif_trdy_reg_in),
|
.wbu_pciif_trdy_reg_in (wbu_pciif_trdy_reg_in),
|
.wbu_pciif_stop_reg_in (wbu_pciif_stop_reg_in),
|
.wbu_pciif_stop_reg_in (wbu_pciif_stop_reg_in),
|
.wbu_pciif_devsel_reg_in (wbu_pciif_devsel_reg_in)
|
.wbu_pciif_devsel_reg_in (wbu_pciif_devsel_reg_in)
|
);
|
);
|
|
|
| Line 778... |
Line 799... |
|
|
wire pciu_mem_enable_in = conf_mem_space_enable_out ;
|
wire pciu_mem_enable_in = conf_mem_space_enable_out ;
|
wire pciu_io_enable_in = conf_io_space_enable_out ;
|
wire pciu_io_enable_in = conf_io_space_enable_out ;
|
|
|
wire pciu_wbw_fifo_empty_in = wbu_wbw_fifo_empty_out ;
|
wire pciu_wbw_fifo_empty_in = wbu_wbw_fifo_empty_out ;
|
|
wire pciu_wbu_del_read_comp_pending_in = wbu_del_read_comp_pending_out ;
|
wire pciu_wbu_frame_en_in = out_bckp_frame_en_out ;
|
wire pciu_wbu_frame_en_in = out_bckp_frame_en_out ;
|
|
|
`ifdef HOST
|
`ifdef HOST
|
wire [31:0] pciu_conf_data_in = conf_r_data_out ;
|
wire [31:0] pciu_conf_data_in = conf_r_data_out ;
|
`else
|
`else
|
`ifdef GUEST
|
`ifdef GUEST
|
wire [31:0] pciu_conf_data_in = conf_w_data_out ;
|
wire [31:0] pciu_conf_data_in = conf_w_data_out ;
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_bar0_in = conf_pci_ba0_out[19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] ;
|
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_bar0_in = conf_pci_ba0_out ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_bar1_in = conf_pci_ba1_out[19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] ;
|
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_bar1_in = conf_pci_ba1_out ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_bar2_in = conf_pci_ba2_out[19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] ;
|
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_bar2_in = conf_pci_ba2_out ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_bar3_in = conf_pci_ba3_out[19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] ;
|
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_bar3_in = conf_pci_ba3_out ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_bar4_in = conf_pci_ba4_out[19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] ;
|
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_bar4_in = conf_pci_ba4_out ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_bar5_in = conf_pci_ba5_out[19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] ;
|
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_bar5_in = conf_pci_ba5_out ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_am0_in = conf_pci_am0_out[19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] ;
|
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_am0_in = conf_pci_am0_out ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_am1_in = conf_pci_am1_out[19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] ;
|
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_am1_in = conf_pci_am1_out ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_am2_in = conf_pci_am2_out[19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] ;
|
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_am2_in = conf_pci_am2_out ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_am3_in = conf_pci_am3_out[19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] ;
|
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_am3_in = conf_pci_am3_out ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_am4_in = conf_pci_am4_out[19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] ;
|
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_am4_in = conf_pci_am4_out ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_am5_in = conf_pci_am5_out[19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] ;
|
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_am5_in = conf_pci_am5_out ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_ta0_in = conf_pci_ta0_out[19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] ;
|
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_ta0_in = conf_pci_ta0_out ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_ta1_in = conf_pci_ta1_out[19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] ;
|
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_ta1_in = conf_pci_ta1_out ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_ta2_in = conf_pci_ta2_out[19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] ;
|
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_ta2_in = conf_pci_ta2_out ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_ta3_in = conf_pci_ta3_out[19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] ;
|
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_ta3_in = conf_pci_ta3_out ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_ta4_in = conf_pci_ta4_out[19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] ;
|
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_ta4_in = conf_pci_ta4_out ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_ta5_in = conf_pci_ta5_out[19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] ;
|
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_ta5_in = conf_pci_ta5_out ;
|
|
|
wire [7:0] pciu_cache_line_size_in = conf_cache_line_size_out ;
|
wire [7:0] pciu_cache_line_size_in = conf_cache_line_size_to_wb_out ;
|
|
wire pciu_cache_lsize_not_zero_in = conf_cache_lsize_not_zero_to_wb_out ;
|
|
|
wire pciu_pciif_frame_in = PCI_FRAMEn_IN ;
|
wire pciu_pciif_frame_in = PCI_FRAMEn_IN ;
|
wire pciu_pciif_irdy_in = PCI_IRDYn_IN ;
|
wire pciu_pciif_irdy_in = PCI_IRDYn_IN ;
|
wire pciu_pciif_idsel_in = PCI_IDSEL_IN ;
|
wire pciu_pciif_idsel_in = PCI_IDSEL_IN ;
|
wire pciu_pciif_frame_reg_in = in_reg_frame_out ;
|
wire pciu_pciif_frame_reg_in = in_reg_frame_out ;
|
| Line 822... |
Line 845... |
|
|
wire pciu_pciif_bckp_trdy_en_in = out_bckp_trdy_en_out ;
|
wire pciu_pciif_bckp_trdy_en_in = out_bckp_trdy_en_out ;
|
wire pciu_pciif_bckp_devsel_in = out_bckp_devsel_out ;
|
wire pciu_pciif_bckp_devsel_in = out_bckp_devsel_out ;
|
wire pciu_pciif_bckp_trdy_in = out_bckp_trdy_out ;
|
wire pciu_pciif_bckp_trdy_in = out_bckp_trdy_out ;
|
wire pciu_pciif_bckp_stop_in = out_bckp_stop_out ;
|
wire pciu_pciif_bckp_stop_in = out_bckp_stop_out ;
|
|
wire pciu_pciif_trdy_reg_in = in_reg_trdy_out ;
|
|
wire pciu_pciif_stop_reg_in = in_reg_stop_out ;
|
wire pciu_err_pending_in = conf_pci_err_pending_out ;
|
|
|
|
PCI_TARGET_UNIT pci_target_unit
|
PCI_TARGET_UNIT pci_target_unit
|
(
|
(
|
.reset_in (reset),
|
.reset_in (reset),
|
.wb_clock_in (wb_clk),
|
.wb_clock_in (wb_clk),
|
| Line 848... |
Line 870... |
.pciu_io_enable_in (pciu_io_enable_in),
|
.pciu_io_enable_in (pciu_io_enable_in),
|
.pciu_map_in (pciu_map_in),
|
.pciu_map_in (pciu_map_in),
|
.pciu_pref_en_in (pciu_pref_en_in),
|
.pciu_pref_en_in (pciu_pref_en_in),
|
.pciu_conf_data_in (pciu_conf_data_in),
|
.pciu_conf_data_in (pciu_conf_data_in),
|
.pciu_wbw_fifo_empty_in (pciu_wbw_fifo_empty_in),
|
.pciu_wbw_fifo_empty_in (pciu_wbw_fifo_empty_in),
|
|
.pciu_wbu_del_read_comp_pending_in (pciu_wbu_del_read_comp_pending_in),
|
.pciu_wbu_frame_en_in (pciu_wbu_frame_en_in),
|
.pciu_wbu_frame_en_in (pciu_wbu_frame_en_in),
|
.pciu_bar0_in (pciu_bar0_in),
|
.pciu_bar0_in (pciu_bar0_in),
|
.pciu_bar1_in (pciu_bar1_in),
|
.pciu_bar1_in (pciu_bar1_in),
|
.pciu_bar2_in (pciu_bar2_in),
|
.pciu_bar2_in (pciu_bar2_in),
|
.pciu_bar3_in (pciu_bar3_in),
|
.pciu_bar3_in (pciu_bar3_in),
|
| Line 869... |
Line 892... |
.pciu_ta3_in (pciu_ta3_in),
|
.pciu_ta3_in (pciu_ta3_in),
|
.pciu_ta4_in (pciu_ta4_in),
|
.pciu_ta4_in (pciu_ta4_in),
|
.pciu_ta5_in (pciu_ta5_in),
|
.pciu_ta5_in (pciu_ta5_in),
|
.pciu_at_en_in (pciu_at_en_in),
|
.pciu_at_en_in (pciu_at_en_in),
|
.pciu_cache_line_size_in (pciu_cache_line_size_in),
|
.pciu_cache_line_size_in (pciu_cache_line_size_in),
|
|
.pciu_cache_lsize_not_zero_in (pciu_cache_lsize_not_zero_in),
|
.pciu_pciif_frame_in (pciu_pciif_frame_in),
|
.pciu_pciif_frame_in (pciu_pciif_frame_in),
|
.pciu_pciif_irdy_in (pciu_pciif_irdy_in),
|
.pciu_pciif_irdy_in (pciu_pciif_irdy_in),
|
.pciu_pciif_idsel_in (pciu_pciif_idsel_in),
|
.pciu_pciif_idsel_in (pciu_pciif_idsel_in),
|
.pciu_pciif_frame_reg_in (pciu_pciif_frame_reg_in),
|
.pciu_pciif_frame_reg_in (pciu_pciif_frame_reg_in),
|
.pciu_pciif_irdy_reg_in (pciu_pciif_irdy_reg_in),
|
.pciu_pciif_irdy_reg_in (pciu_pciif_irdy_reg_in),
|
| Line 881... |
Line 905... |
.pciu_pciif_cbe_reg_in (pciu_pciif_cbe_reg_in),
|
.pciu_pciif_cbe_reg_in (pciu_pciif_cbe_reg_in),
|
.pciu_pciif_bckp_trdy_en_in (pciu_pciif_bckp_trdy_en_in),
|
.pciu_pciif_bckp_trdy_en_in (pciu_pciif_bckp_trdy_en_in),
|
.pciu_pciif_bckp_devsel_in (pciu_pciif_bckp_devsel_in),
|
.pciu_pciif_bckp_devsel_in (pciu_pciif_bckp_devsel_in),
|
.pciu_pciif_bckp_trdy_in (pciu_pciif_bckp_trdy_in),
|
.pciu_pciif_bckp_trdy_in (pciu_pciif_bckp_trdy_in),
|
.pciu_pciif_bckp_stop_in (pciu_pciif_bckp_stop_in),
|
.pciu_pciif_bckp_stop_in (pciu_pciif_bckp_stop_in),
|
|
.pciu_pciif_trdy_reg_in (pciu_pciif_trdy_reg_in),
|
|
.pciu_pciif_stop_reg_in (pciu_pciif_stop_reg_in),
|
.pciu_pciif_trdy_out (pciu_pciif_trdy_out),
|
.pciu_pciif_trdy_out (pciu_pciif_trdy_out),
|
.pciu_pciif_stop_out (pciu_pciif_stop_out),
|
.pciu_pciif_stop_out (pciu_pciif_stop_out),
|
.pciu_pciif_devsel_out (pciu_pciif_devsel_out),
|
.pciu_pciif_devsel_out (pciu_pciif_devsel_out),
|
.pciu_pciif_trdy_en_out (pciu_pciif_trdy_en_out),
|
.pciu_pciif_trdy_en_out (pciu_pciif_trdy_en_out),
|
.pciu_pciif_stop_en_out (pciu_pciif_stop_en_out),
|
.pciu_pciif_stop_en_out (pciu_pciif_stop_en_out),
|
.pciu_pciif_devsel_en_out (pciu_pciif_devsel_en_out),
|
.pciu_pciif_devsel_en_out (pciu_pciif_devsel_en_out),
|
.pciu_pciif_target_load_out (pciu_pciif_target_load_out),
|
.pciu_ad_load_out (pciu_ad_load_out),
|
|
.pciu_ad_load_on_transfer_out (pciu_ad_load_on_transfer_out),
|
.pciu_pciif_ad_out (pciu_pciif_ad_out),
|
.pciu_pciif_ad_out (pciu_pciif_ad_out),
|
.pciu_pciif_ad_en_out (pciu_pciif_ad_en_out),
|
.pciu_pciif_ad_en_out (pciu_pciif_ad_en_out),
|
.pciu_pciif_tabort_set_out (pciu_pciif_tabort_set_out),
|
.pciu_pciif_tabort_set_out (pciu_pciif_tabort_set_out),
|
.pciu_err_addr_out (pciu_err_addr_out),
|
.pciu_err_addr_out (pciu_err_addr_out),
|
.pciu_err_bc_out (pciu_err_bc_out),
|
.pciu_err_bc_out (pciu_err_bc_out),
|
.pciu_err_data_out (pciu_err_data_out),
|
.pciu_err_data_out (pciu_err_data_out),
|
.pciu_err_be_out (pciu_err_be_out),
|
.pciu_err_be_out (pciu_err_be_out),
|
.pciu_err_signal_out (pciu_err_signal_out),
|
.pciu_err_signal_out (pciu_err_signal_out),
|
.pciu_err_source_out (pciu_err_source_out),
|
.pciu_err_source_out (pciu_err_source_out),
|
.pciu_err_rty_exp_out (pciu_err_rty_exp_out),
|
.pciu_err_rty_exp_out (pciu_err_rty_exp_out),
|
.pciu_err_pending_in (pciu_err_pending_in),
|
|
.pciu_conf_offset_out (pciu_conf_offset_out),
|
.pciu_conf_offset_out (pciu_conf_offset_out),
|
.pciu_conf_renable_out (pciu_conf_renable_out),
|
.pciu_conf_renable_out (pciu_conf_renable_out),
|
.pciu_conf_wenable_out (pciu_conf_wenable_out),
|
.pciu_conf_wenable_out (pciu_conf_wenable_out),
|
.pciu_conf_be_out (pciu_conf_be_out),
|
.pciu_conf_be_out (pciu_conf_be_out),
|
.pciu_conf_data_out (pciu_conf_data_out),
|
.pciu_conf_data_out (pciu_conf_data_out),
|
| Line 948... |
Line 974... |
|
|
wire conf_master_data_par_err_in = parchk_perr_mas_detect_out ;
|
wire conf_master_data_par_err_in = parchk_perr_mas_detect_out ;
|
|
|
wire [3:0] conf_pci_err_be_in = pciu_err_be_out ;
|
wire [3:0] conf_pci_err_be_in = pciu_err_be_out ;
|
wire [3:0] conf_pci_err_bc_in = pciu_err_bc_out;
|
wire [3:0] conf_pci_err_bc_in = pciu_err_bc_out;
|
|
wire conf_pci_err_es_in = pciu_err_source_out ;
|
wire conf_pci_err_rty_exp_in = pciu_err_rty_exp_out ;
|
wire conf_pci_err_rty_exp_in = pciu_err_rty_exp_out ;
|
wire conf_pci_err_sig_in = pciu_err_signal_out ;
|
wire conf_pci_err_sig_in = pciu_err_signal_out ;
|
wire [31:0] conf_pci_err_addr_in = pciu_err_addr_out ;
|
wire [31:0] conf_pci_err_addr_in = pciu_err_addr_out ;
|
wire [31:0] conf_pci_err_data_in = pciu_err_data_out ;
|
wire [31:0] conf_pci_err_data_in = pciu_err_data_out ;
|
|
|
| Line 961... |
Line 988... |
wire conf_wb_err_es_in = wbu_err_source_out ;
|
wire conf_wb_err_es_in = wbu_err_source_out ;
|
wire conf_wb_err_sig_in = wbu_err_signal_out ;
|
wire conf_wb_err_sig_in = wbu_err_signal_out ;
|
wire [31:0] conf_wb_err_addr_in = wbu_err_addr_out ;
|
wire [31:0] conf_wb_err_addr_in = wbu_err_addr_out ;
|
wire [31:0] conf_wb_err_data_in = out_bckp_ad_out ;
|
wire [31:0] conf_wb_err_data_in = out_bckp_ad_out ;
|
|
|
/////////////////////////////////////////////////////////////////////////////////////////////////
|
wire conf_isr_int_prop_in = pci_into_conf_isr_int_prop_out ;
|
// Interrupts not implemented yet
|
wire conf_par_err_int_in = parchk_perr_mas_detect_out ;
|
wire conf_isr_int_prop_in = 1'b0 ;
|
wire conf_sys_err_int_in = parchk_sig_serr_out ;
|
wire conf_isr_err_int_in = 1'b0 ;
|
|
wire conf_par_err_int_in = 1'b0 ;
|
|
wire conf_sys_err_int_in = 1'b0 ;
|
|
/////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
CONF_SPACE configuration (
|
CONF_SPACE configuration (
|
.reset (reset),
|
.reset (reset),
|
.pci_clk (pci_clk),
|
.pci_clk (pci_clk),
|
.wb_clk (wb_clk),
|
.wb_clk (wb_clk),
|
| Line 994... |
Line 1017... |
.serr_in (conf_serr_in),
|
.serr_in (conf_serr_in),
|
.master_abort_recv (conf_master_abort_recv_in),
|
.master_abort_recv (conf_master_abort_recv_in),
|
.target_abort_recv (conf_target_abort_recv_in),
|
.target_abort_recv (conf_target_abort_recv_in),
|
.target_abort_set (conf_target_abort_set_in),
|
.target_abort_set (conf_target_abort_set_in),
|
.master_data_par_err (conf_master_data_par_err_in),
|
.master_data_par_err (conf_master_data_par_err_in),
|
.cache_line_size (conf_cache_line_size_out),
|
.cache_line_size_to_pci (conf_cache_line_size_to_pci_out),
|
|
.cache_line_size_to_wb (conf_cache_line_size_to_wb_out),
|
|
.cache_lsize_not_zero_to_wb (conf_cache_lsize_not_zero_to_wb_out),
|
.latency_tim (conf_latency_tim_out),
|
.latency_tim (conf_latency_tim_out),
|
.int_pin (conf_int_pin_out),
|
|
.pci_base_addr0 (conf_pci_ba0_out),
|
.pci_base_addr0 (conf_pci_ba0_out),
|
.pci_base_addr1 (conf_pci_ba1_out),
|
.pci_base_addr1 (conf_pci_ba1_out),
|
.pci_base_addr2 (conf_pci_ba2_out),
|
.pci_base_addr2 (conf_pci_ba2_out),
|
.pci_base_addr3 (conf_pci_ba3_out),
|
.pci_base_addr3 (conf_pci_ba3_out),
|
.pci_base_addr4 (conf_pci_ba4_out),
|
.pci_base_addr4 (conf_pci_ba4_out),
|
| Line 1030... |
Line 1054... |
.pci_img_ctrl4 (conf_pci_img_ctrl4_out),
|
.pci_img_ctrl4 (conf_pci_img_ctrl4_out),
|
.pci_img_ctrl5 (conf_pci_img_ctrl5_out),
|
.pci_img_ctrl5 (conf_pci_img_ctrl5_out),
|
.pci_error_be (conf_pci_err_be_in),
|
.pci_error_be (conf_pci_err_be_in),
|
.pci_error_bc (conf_pci_err_bc_in),
|
.pci_error_bc (conf_pci_err_bc_in),
|
.pci_error_rty_exp (conf_pci_err_rty_exp_in),
|
.pci_error_rty_exp (conf_pci_err_rty_exp_in),
|
|
.pci_error_es (conf_pci_err_es_in),
|
.pci_error_sig (conf_pci_err_sig_in),
|
.pci_error_sig (conf_pci_err_sig_in),
|
.pci_error_addr (conf_pci_err_addr_in),
|
.pci_error_addr (conf_pci_err_addr_in),
|
.pci_error_data (conf_pci_err_data_in),
|
.pci_error_data (conf_pci_err_data_in),
|
.pci_error_rty_exp_set (conf_pci_err_rty_exp_out),
|
|
.pci_error_en (conf_pci_error_en_out),
|
|
.wb_base_addr0 (conf_wb_ba0_out),
|
.wb_base_addr0 (conf_wb_ba0_out),
|
.wb_base_addr1 (conf_wb_ba1_out),
|
.wb_base_addr1 (conf_wb_ba1_out),
|
.wb_base_addr2 (conf_wb_ba2_out),
|
.wb_base_addr2 (conf_wb_ba2_out),
|
.wb_base_addr3 (conf_wb_ba3_out),
|
.wb_base_addr3 (conf_wb_ba3_out),
|
.wb_base_addr4 (conf_wb_ba4_out),
|
.wb_base_addr4 (conf_wb_ba4_out),
|
| Line 1072... |
Line 1095... |
.wb_error_rty_exp (conf_wb_err_rty_exp_in),
|
.wb_error_rty_exp (conf_wb_err_rty_exp_in),
|
.wb_error_es (conf_wb_err_es_in),
|
.wb_error_es (conf_wb_err_es_in),
|
.wb_error_sig (conf_wb_err_sig_in),
|
.wb_error_sig (conf_wb_err_sig_in),
|
.wb_error_addr (conf_wb_err_addr_in),
|
.wb_error_addr (conf_wb_err_addr_in),
|
.wb_error_data (conf_wb_err_data_in),
|
.wb_error_data (conf_wb_err_data_in),
|
.wb_error_rty_exp_set (conf_wb_err_rty_exp_out),
|
|
.wb_error_en (conf_wb_err_en_out),
|
|
.config_addr (conf_ccyc_addr_out),
|
.config_addr (conf_ccyc_addr_out),
|
.icr_soft_res (conf_soft_res_out),
|
.icr_soft_res (conf_soft_res_out),
|
.serr_int_en (conf_serr_int_en_out),
|
.int_out (conf_int_out),
|
.perr_int_en (conf_perr_int_en_out),
|
|
.error_int_en (conf_err_int_en_out),
|
|
.int_prop_en (conf_int_prop_en_out),
|
|
.isr_int_prop (conf_isr_int_prop_in),
|
.isr_int_prop (conf_isr_int_prop_in),
|
.isr_err_int (conf_isr_err_int_in),
|
|
.isr_par_err_int (conf_par_err_int_in),
|
.isr_par_err_int (conf_par_err_int_in),
|
.isr_sys_err_int (conf_sys_err_int_in),
|
.isr_sys_err_int (conf_sys_err_int_in)
|
.pci_error_sig_set (conf_pci_err_pending_out),
|
|
.wb_error_sig_set (conf_wb_err_pending_out)
|
|
) ;
|
) ;
|
|
|
// pci data io multiplexer inputs
|
// pci data io multiplexer inputs
|
wire pci_mux_tar_ad_en_in = pciu_pciif_ad_en_out ;
|
wire pci_mux_tar_ad_en_in = pciu_pciif_ad_en_out ;
|
wire pci_mux_tar_ad_en_reg_in = out_bckp_tar_ad_en_out ;
|
wire pci_mux_tar_ad_en_reg_in = out_bckp_tar_ad_en_out ;
|
| Line 1098... |
Line 1113... |
wire pci_mux_devsel_en_in = pciu_pciif_devsel_en_out ;
|
wire pci_mux_devsel_en_in = pciu_pciif_devsel_en_out ;
|
wire pci_mux_trdy_in = pciu_pciif_trdy_out ;
|
wire pci_mux_trdy_in = pciu_pciif_trdy_out ;
|
wire pci_mux_trdy_en_in = pciu_pciif_trdy_en_out ;
|
wire pci_mux_trdy_en_in = pciu_pciif_trdy_en_out ;
|
wire pci_mux_stop_in = pciu_pciif_stop_out ;
|
wire pci_mux_stop_in = pciu_pciif_stop_out ;
|
wire pci_mux_stop_en_in = pciu_pciif_stop_en_out ;
|
wire pci_mux_stop_en_in = pciu_pciif_stop_en_out ;
|
wire pci_mux_tar_load_in = pciu_pciif_target_load_out ;
|
wire pci_mux_tar_load_in = pciu_ad_load_out ;
|
|
wire pci_mux_tar_load_on_transfer_in = pciu_ad_load_on_transfer_out ;
|
|
|
wire pci_mux_mas_ad_en_in = wbu_pciif_ad_en_out ;
|
wire pci_mux_mas_ad_en_in = wbu_pciif_ad_en_out ;
|
wire [31:0] pci_mux_mas_ad_in = wbu_pciif_ad_out ;
|
wire [31:0] pci_mux_mas_ad_in = wbu_pciif_ad_out ;
|
|
|
wire pci_mux_frame_in = wbu_pciif_frame_out ;
|
wire pci_mux_frame_in = wbu_pciif_frame_out ;
|
wire pci_mux_frame_en_in = wbu_pciif_frame_en_out ;
|
wire pci_mux_frame_en_in = wbu_pciif_frame_en_out ;
|
wire pci_mux_irdy_in = wbu_pciif_irdy_out;
|
wire pci_mux_irdy_in = wbu_pciif_irdy_out;
|
wire pci_mux_irdy_en_in = wbu_pciif_irdy_en_out;
|
wire pci_mux_irdy_en_in = wbu_pciif_irdy_en_out;
|
wire pci_mux_mas_load_in = wbu_pciif_load_next_out ;
|
wire pci_mux_mas_load_in = wbu_ad_load_out ;
|
|
wire pci_mux_mas_load_on_transfer_in = wbu_ad_load_on_transfer_out ;
|
wire [3:0] pci_mux_cbe_in = wbu_pciif_cbe_out ;
|
wire [3:0] pci_mux_cbe_in = wbu_pciif_cbe_out ;
|
wire pci_mux_cbe_en_in = wbu_pciif_cbe_en_out ;
|
wire pci_mux_cbe_en_in = wbu_pciif_cbe_en_out ;
|
|
|
wire pci_mux_par_in = parchk_pci_par_out ;
|
wire pci_mux_par_in = parchk_pci_par_out ;
|
wire pci_mux_par_en_in = parchk_pci_par_en_out ;
|
wire pci_mux_par_en_in = parchk_pci_par_en_out ;
|
| Line 1121... |
Line 1138... |
wire pci_mux_serr_en_in = parchk_pci_serr_en_out;
|
wire pci_mux_serr_en_in = parchk_pci_serr_en_out;
|
|
|
wire pci_mux_req_in = wbu_pciif_req_out ;
|
wire pci_mux_req_in = wbu_pciif_req_out ;
|
wire pci_mux_frame_load_in = wbu_pciif_frame_load_out ;
|
wire pci_mux_frame_load_in = wbu_pciif_frame_load_out ;
|
|
|
|
wire pci_mux_pci_irdy_in = PCI_IRDYn_IN ;
|
|
wire pci_mux_pci_trdy_in = PCI_TRDYn_IN ;
|
|
wire pci_mux_pci_frame_in = PCI_FRAMEn_IN ;
|
|
wire pci_mux_pci_stop_in = PCI_STOPn_IN ;
|
|
|
PCI_IO_MUX pci_io_mux
|
PCI_IO_MUX pci_io_mux
|
(
|
(
|
.reset_in (reset),
|
.reset_in (reset),
|
.clk_in (pci_clk),
|
.clk_in (pci_clk),
|
.frame_in (pci_mux_frame_in),
|
.frame_in (pci_mux_frame_in),
|
| Line 1137... |
Line 1159... |
.trdy_in (pci_mux_trdy_in),
|
.trdy_in (pci_mux_trdy_in),
|
.trdy_en_in (pci_mux_trdy_en_in),
|
.trdy_en_in (pci_mux_trdy_en_in),
|
.stop_in (pci_mux_stop_in),
|
.stop_in (pci_mux_stop_in),
|
.stop_en_in (pci_mux_stop_en_in),
|
.stop_en_in (pci_mux_stop_en_in),
|
.master_load_in (pci_mux_mas_load_in),
|
.master_load_in (pci_mux_mas_load_in),
|
|
.master_load_on_transfer_in (pci_mux_mas_load_on_transfer_in),
|
.target_load_in (pci_mux_tar_load_in),
|
.target_load_in (pci_mux_tar_load_in),
|
|
.target_load_on_transfer_in (pci_mux_tar_load_on_transfer_in),
|
.cbe_in (pci_mux_cbe_in),
|
.cbe_in (pci_mux_cbe_in),
|
.cbe_en_in (pci_mux_cbe_en_in),
|
.cbe_en_in (pci_mux_cbe_en_in),
|
.mas_ad_in (pci_mux_mas_ad_in),
|
.mas_ad_in (pci_mux_mas_ad_in),
|
.tar_ad_in (pci_mux_tar_ad_in),
|
.tar_ad_in (pci_mux_tar_ad_in),
|
|
|
| Line 1169... |
Line 1193... |
.devsel_out (pci_mux_devsel_out),
|
.devsel_out (pci_mux_devsel_out),
|
.trdy_out (pci_mux_trdy_out),
|
.trdy_out (pci_mux_trdy_out),
|
.stop_out (pci_mux_stop_out),
|
.stop_out (pci_mux_stop_out),
|
.cbe_out (pci_mux_cbe_out),
|
.cbe_out (pci_mux_cbe_out),
|
.ad_out (pci_mux_ad_out),
|
.ad_out (pci_mux_ad_out),
|
|
.ad_load_out (pci_mux_ad_load_out),
|
|
|
.par_out (pci_mux_par_out),
|
.par_out (pci_mux_par_out),
|
.par_en_out (pci_mux_par_en_out),
|
.par_en_out (pci_mux_par_en_out),
|
.perr_out (pci_mux_perr_out),
|
.perr_out (pci_mux_perr_out),
|
.perr_en_out (pci_mux_perr_en_out),
|
.perr_en_out (pci_mux_perr_en_out),
|
.serr_out (pci_mux_serr_out),
|
.serr_out (pci_mux_serr_out),
|
.serr_en_out (pci_mux_serr_en_out),
|
.serr_en_out (pci_mux_serr_en_out),
|
.req_in (pci_mux_req_in),
|
.req_in (pci_mux_req_in),
|
.req_out (pci_mux_req_out),
|
.req_out (pci_mux_req_out),
|
.req_en_out (pci_mux_req_en_out)
|
.req_en_out (pci_mux_req_en_out),
|
|
.pci_irdy_in (pci_mux_pci_irdy_in),
|
|
.pci_trdy_in (pci_mux_pci_trdy_in),
|
|
.pci_frame_in (pci_mux_pci_frame_in),
|
|
.pci_stop_in (pci_mux_pci_stop_in),
|
|
.ad_en_unregistered_out (pci_mux_ad_en_unregistered_out)
|
);
|
);
|
|
|
CUR_OUT_REG output_backup
|
CUR_OUT_REG output_backup
|
(
|
(
|
.reset_in (reset),
|
.reset_in (reset),
|
| Line 1194... |
Line 1224... |
.irdy_en_in (pci_mux_irdy_en_in),
|
.irdy_en_in (pci_mux_irdy_en_in),
|
.devsel_in (pci_mux_devsel_in),
|
.devsel_in (pci_mux_devsel_in),
|
.trdy_in (pci_mux_trdy_in),
|
.trdy_in (pci_mux_trdy_in),
|
.trdy_en_in (pci_mux_trdy_en_in),
|
.trdy_en_in (pci_mux_trdy_en_in),
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.stop_in (pci_mux_stop_in),
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.stop_in (pci_mux_stop_in),
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.master_load_in (pci_mux_mas_load_in),
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.ad_load_in (pci_mux_ad_load_out),
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.target_load_in (pci_mux_tar_load_in),
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.cbe_in (pci_mux_cbe_in),
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.cbe_in (pci_mux_cbe_in),
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.cbe_en_in (pci_mux_cbe_en_in),
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.cbe_en_in (pci_mux_cbe_en_in),
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.mas_ad_in (pci_mux_mas_ad_in),
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.mas_ad_in (pci_mux_mas_ad_in),
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.tar_ad_in (pci_mux_tar_ad_in),
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.tar_ad_in (pci_mux_tar_ad_in),
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.mas_ad_en_in (pci_mux_mas_ad_en_in),
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.mas_ad_en_in (pci_mux_mas_ad_en_in),
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.tar_ad_en_in (pci_mux_tar_ad_en_in),
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.tar_ad_en_in (pci_mux_tar_ad_en_in),
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.ad_en_unregistered_in (pci_mux_ad_en_unregistered_out),
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.par_in (pci_mux_par_in),
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.par_in (pci_mux_par_in),
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.par_en_in (pci_mux_par_en_in),
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.par_en_in (pci_mux_par_en_in),
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.perr_in (pci_mux_perr_in),
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.perr_in (pci_mux_perr_in),
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.perr_en_in (pci_mux_perr_en_in),
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.perr_en_in (pci_mux_perr_en_in),
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| Line 1250... |
Line 1280... |
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wire [31:0] parchk_pci_ad_out_in = out_bckp_ad_out ;
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wire [31:0] parchk_pci_ad_out_in = out_bckp_ad_out ;
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wire [31:0] parchk_pci_ad_reg_in = in_reg_ad_out ;
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wire [31:0] parchk_pci_ad_reg_in = in_reg_ad_out ;
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wire [3:0] parchk_pci_cbe_in_in = PCI_CBEn_IN ;
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wire [3:0] parchk_pci_cbe_in_in = PCI_CBEn_IN ;
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wire [3:0] parchk_pci_cbe_reg_in = in_reg_cbe_out ;
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wire [3:0] parchk_pci_cbe_out_in = out_bckp_cbe_out ;
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wire [3:0] parchk_pci_cbe_out_in = out_bckp_cbe_out ;
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wire parchk_pci_ad_en_in = out_bckp_ad_en_out ;
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wire parchk_pci_ad_en_in = out_bckp_ad_en_out ;
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wire parchk_par_err_response_in = conf_perr_response_out ;
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wire parchk_par_err_response_in = conf_perr_response_out ;
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wire parchk_serr_enable_in = conf_serr_enable_out ;
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wire parchk_serr_enable_in = conf_serr_enable_out ;
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| Line 1287... |
Line 1318... |
.pci_trdy_reg_in (parchk_pci_trdy_reg_in),
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.pci_trdy_reg_in (parchk_pci_trdy_reg_in),
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.pci_trdy_en_in (parchk_pci_trdy_en_in),
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.pci_trdy_en_in (parchk_pci_trdy_en_in),
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.pci_ad_out_in (parchk_pci_ad_out_in),
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.pci_ad_out_in (parchk_pci_ad_out_in),
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.pci_ad_reg_in (parchk_pci_ad_reg_in),
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.pci_ad_reg_in (parchk_pci_ad_reg_in),
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.pci_cbe_in_in (parchk_pci_cbe_in_in),
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.pci_cbe_in_in (parchk_pci_cbe_in_in),
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.pci_cbe_reg_in (parchk_pci_cbe_reg_in),
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.pci_cbe_en_in (parchk_pci_cbe_en_in),
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.pci_cbe_en_in (parchk_pci_cbe_en_in),
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.pci_cbe_out_in (parchk_pci_cbe_out_in),
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.pci_cbe_out_in (parchk_pci_cbe_out_in),
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.pci_ad_en_in (parchk_pci_ad_en_in),
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.pci_ad_en_in (parchk_pci_ad_en_in),
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.par_err_response_in (parchk_par_err_response_in),
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.par_err_response_in (parchk_par_err_response_in),
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.par_err_detect_out (parchk_par_err_detect_out),
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.par_err_detect_out (parchk_par_err_detect_out),
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.perr_mas_detect_out (parchk_perr_mas_detect_out),
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.perr_mas_detect_out (parchk_perr_mas_detect_out),
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.serr_enable_in (parchk_serr_enable_in),
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.serr_enable_in (parchk_serr_enable_in),
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.sig_serr_out (parchk_sig_serr_out)
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.sig_serr_out (parchk_sig_serr_out)
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|
|
);
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);
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|
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wire in_reg_gnt_in = PCI_GNTn_IN ;
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wire in_reg_gnt_in = PCI_GNTn_IN ;
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wire in_reg_frame_in = PCI_FRAMEn_IN ;
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wire in_reg_frame_in = PCI_FRAMEn_IN ;
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wire in_reg_irdy_in = PCI_IRDYn_IN ;
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wire in_reg_irdy_in = PCI_IRDYn_IN ;
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| Line 1335... |
Line 1366... |
.pci_ad_reg_out (in_reg_ad_out),
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.pci_ad_reg_out (in_reg_ad_out),
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.pci_cbe_reg_out (in_reg_cbe_out)
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.pci_cbe_reg_out (in_reg_cbe_out)
|
);
|
);
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|
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endmodule
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endmodule
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