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Line 41... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/02/01 15:25:12 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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//
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// Revision 1.2 2001/10/05 08:14:28 mihad
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// Revision 1.2 2001/10/05 08:14:28 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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//
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// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
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// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
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// New project directory structure
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// New project directory structure
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| Line 154... |
Line 157... |
PCI_PERRn_EN_OUT,
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PCI_PERRn_EN_OUT,
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// system error pin
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// system error pin
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PCI_SERRn_OUT,
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PCI_SERRn_OUT,
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PCI_SERRn_EN_OUT
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PCI_SERRn_EN_OUT
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`ifdef PCI_BIST
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,
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// debug chain signals
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SO ,
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SI ,
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shift_DR ,
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capture_DR ,
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extest ,
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tck
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`endif
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);
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);
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// WISHBONE system signals
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// WISHBONE system signals
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input CLK_I ;
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input CLK_I ;
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input RST_I ;
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input RST_I ;
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| Line 250... |
Line 264... |
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// system error pin
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// system error pin
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output PCI_SERRn_OUT ;
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output PCI_SERRn_OUT ;
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output PCI_SERRn_EN_OUT ;
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output PCI_SERRn_EN_OUT ;
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`ifdef PCI_BIST
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/*-----------------------------------------------------
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BIST debug chain port signals
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-----------------------------------------------------*/
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output SO ;
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input SI ;
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input shift_DR ;
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input capture_DR ;
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input extest ;
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input tck ;
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// internal wires for serial chain connection
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wire SO_internal ;
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wire SI_internal = SO_internal ;
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`endif
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// declare clock and reset wires
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// declare clock and reset wires
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wire pci_clk = PCI_CLK_IN ;
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wire pci_clk = PCI_CLK_IN ;
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wire wb_clk = CLK_I ;
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wire wb_clk = CLK_I ;
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wire reset ; // assigned at pci bridge reset and interrupt logic
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wire reset ; // assigned at pci bridge reset and interrupt logic
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| Line 760... |
Line 790... |
.wbu_ad_load_out (wbu_ad_load_out),
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.wbu_ad_load_out (wbu_ad_load_out),
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.wbu_ad_load_on_transfer_out (wbu_ad_load_on_transfer_out),
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.wbu_ad_load_on_transfer_out (wbu_ad_load_on_transfer_out),
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.wbu_pciif_trdy_reg_in (wbu_pciif_trdy_reg_in),
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.wbu_pciif_trdy_reg_in (wbu_pciif_trdy_reg_in),
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.wbu_pciif_stop_reg_in (wbu_pciif_stop_reg_in),
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.wbu_pciif_stop_reg_in (wbu_pciif_stop_reg_in),
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.wbu_pciif_devsel_reg_in (wbu_pciif_devsel_reg_in)
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.wbu_pciif_devsel_reg_in (wbu_pciif_devsel_reg_in)
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`ifdef PCI_BIST
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,
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.SO (SO_internal),
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.SI (SI),
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.shift_DR (shift_DR),
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.capture_DR (capture_DR),
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.extest (extest),
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.tck (tck)
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`endif
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);
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);
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// PCI TARGET UNIT INPUTS
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// PCI TARGET UNIT INPUTS
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wire [31:0] pciu_mdata_in = MDAT_I ;
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wire [31:0] pciu_mdata_in = MDAT_I ;
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wire pciu_ack_in = ACK_I ;
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wire pciu_ack_in = ACK_I ;
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| Line 933... |
Line 973... |
.pciu_conf_be_out (pciu_conf_be_out),
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.pciu_conf_be_out (pciu_conf_be_out),
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.pciu_conf_data_out (pciu_conf_data_out),
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.pciu_conf_data_out (pciu_conf_data_out),
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.pciu_conf_select_out (pciu_conf_select_out),
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.pciu_conf_select_out (pciu_conf_select_out),
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.pciu_pci_drcomp_pending_out (pciu_pci_drcomp_pending_out),
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.pciu_pci_drcomp_pending_out (pciu_pci_drcomp_pending_out),
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.pciu_pciw_fifo_empty_out (pciu_pciw_fifo_empty_out)
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.pciu_pciw_fifo_empty_out (pciu_pciw_fifo_empty_out)
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`ifdef PCI_BIST
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,
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.SO (SO),
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.SI (SI_internal),
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.shift_DR (shift_DR),
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.capture_DR (capture_DR),
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.extest (extest),
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.tck (tck)
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`endif
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);
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);
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// CONFIGURATION SPACE INPUTS
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// CONFIGURATION SPACE INPUTS
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`ifdef HOST
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`ifdef HOST
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