| Line 41... |
Line 41... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2003/01/27 16:49:31 mihad
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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//
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// Revision 1.4 2002/08/13 11:03:53 mihad
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// Revision 1.4 2002/08/13 11:03:53 mihad
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// Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image
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// Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image
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//
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//
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// Revision 1.3 2002/02/01 15:25:12 mihad
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// Revision 1.3 2002/02/01 15:25:12 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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// Repaired a few bugs, updated specification, added test bench files and design document
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| Line 2457... |
Line 2460... |
set_status_bit15_11[12] && !block_set_status_bit12,
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set_status_bit15_11[12] && !block_set_status_bit12,
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set_status_bit15_11[11] && !block_set_status_bit11,
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set_status_bit15_11[11] && !block_set_status_bit11,
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set_status_bit8 && !block_set_status_bit8 } ;
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set_status_bit8 && !block_set_status_bit8 } ;
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wire [5:0] meta_status_bits ;
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wire [5:0] meta_status_bits ;
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// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
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// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
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synchronizer_flop #(6) status_bits_sync
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synchronizer_flop #(6, 0) status_bits_sync
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(
|
(
|
.data_in (status_bits),
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.data_in (status_bits),
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.clk_out (wb_clk),
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.clk_out (wb_clk),
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.sync_data_out (meta_status_bits),
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.sync_data_out (meta_status_bits),
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.async_reset (reset)
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.async_reset (reset)
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| Line 2619... |
Line 2622... |
end
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end
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end
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end
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wire pci_err_cs_bits = set_pci_err_cs_bit8 && !block_set_pci_err_cs_bit8 ;
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wire pci_err_cs_bits = set_pci_err_cs_bit8 && !block_set_pci_err_cs_bit8 ;
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wire meta_pci_err_cs_bits ;
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wire meta_pci_err_cs_bits ;
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// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
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// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
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synchronizer_flop pci_err_cs_bits_sync
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synchronizer_flop #(1,0) pci_err_cs_bits_sync
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(
|
(
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.data_in (pci_err_cs_bits),
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.data_in (pci_err_cs_bits),
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.clk_out (pci_clk),
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.clk_out (pci_clk),
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.sync_data_out (meta_pci_err_cs_bits),
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.sync_data_out (meta_pci_err_cs_bits),
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.async_reset (reset)
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.async_reset (reset)
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| Line 2721... |
Line 2724... |
end
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end
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end
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end
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wire wb_err_cs_bits = set_wb_err_cs_bit8 && !block_set_wb_err_cs_bit8 ;
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wire wb_err_cs_bits = set_wb_err_cs_bit8 && !block_set_wb_err_cs_bit8 ;
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wire meta_wb_err_cs_bits ;
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wire meta_wb_err_cs_bits ;
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// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
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// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
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synchronizer_flop wb_err_cs_bits_sync
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synchronizer_flop #(1,0) wb_err_cs_bits_sync
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(
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(
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.data_in (wb_err_cs_bits),
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.data_in (wb_err_cs_bits),
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.clk_out (wb_clk),
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.clk_out (wb_clk),
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.sync_data_out (meta_wb_err_cs_bits),
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.sync_data_out (meta_wb_err_cs_bits),
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.async_reset (reset)
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.async_reset (reset)
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| Line 2878... |
Line 2881... |
end
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end
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wire [4:3] isr_bits4_3 = {set_isr_bit4_3[4] && !block_set_isr_bit4,
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wire [4:3] isr_bits4_3 = {set_isr_bit4_3[4] && !block_set_isr_bit4,
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set_isr_bit4_3[3] && !block_set_isr_bit3 } ;
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set_isr_bit4_3[3] && !block_set_isr_bit3 } ;
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wire [4:3] meta_isr_bits4_3 ;
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wire [4:3] meta_isr_bits4_3 ;
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// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
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// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
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synchronizer_flop #(2) isr_bits_sync
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synchronizer_flop #(2, 0) isr_bits_sync
|
(
|
(
|
.data_in (isr_bits4_3),
|
.data_in (isr_bits4_3),
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.clk_out (wb_clk),
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.clk_out (wb_clk),
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.sync_data_out (meta_isr_bits4_3),
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.sync_data_out (meta_isr_bits4_3),
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.async_reset (reset)
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.async_reset (reset)
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| Line 2957... |
Line 2960... |
end
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end
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end
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end
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wire isr_bit1 = set_isr_bit1 && !block_set_isr_bit1 ;
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wire isr_bit1 = set_isr_bit1 && !block_set_isr_bit1 ;
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wire meta_isr_bit1 ;
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wire meta_isr_bit1 ;
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// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
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// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
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synchronizer_flop isr_bit1_sync
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synchronizer_flop #(1, 0) isr_bit1_sync
|
(
|
(
|
.data_in (isr_bit1),
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.data_in (isr_bit1),
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.clk_out (wb_clk),
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.clk_out (wb_clk),
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.sync_data_out (meta_isr_bit1),
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.sync_data_out (meta_isr_bit1),
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.async_reset (reset)
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.async_reset (reset)
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| Line 3030... |
Line 3033... |
end
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end
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end
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end
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wire isr_bit2 = set_isr_bit2 && !block_set_isr_bit2 ;
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wire isr_bit2 = set_isr_bit2 && !block_set_isr_bit2 ;
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wire meta_isr_bit2 ;
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wire meta_isr_bit2 ;
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// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
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// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
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synchronizer_flop isr_bit2_sync
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synchronizer_flop #(1, 0) isr_bit2_sync
|
(
|
(
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.data_in (isr_bit2),
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.data_in (isr_bit2),
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.clk_out (pci_clk),
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.clk_out (pci_clk),
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.sync_data_out (meta_isr_bit2),
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.sync_data_out (meta_isr_bit2),
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.async_reset (reset)
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.async_reset (reset)
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| Line 3052... |
Line 3055... |
// INT BIT of ISR - interrupt status register
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// INT BIT of ISR - interrupt status register
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`ifdef HOST
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`ifdef HOST
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wire isr_int_prop_bit = isr_int_prop && icr_bit2_0[0] ;
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wire isr_int_prop_bit = isr_int_prop && icr_bit2_0[0] ;
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wire meta_isr_int_prop_bit ;
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wire meta_isr_int_prop_bit ;
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// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
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// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
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synchronizer_flop isr_bit0_sync
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synchronizer_flop #(1, 0) isr_bit0_sync
|
(
|
(
|
.data_in (isr_int_prop_bit),
|
.data_in (isr_int_prop_bit),
|
.clk_out (wb_clk),
|
.clk_out (wb_clk),
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.sync_data_out (meta_isr_int_prop_bit),
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.sync_data_out (meta_isr_int_prop_bit),
|
.async_reset (reset)
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.async_reset (reset)
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| Line 3080... |
Line 3083... |
end
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end
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`else // not SYNCHRONEOUS_CLOCK_DOMAINS
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`else // not SYNCHRONEOUS_CLOCK_DOMAINS
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wire isr_int_prop_bit = isr_int_prop && icr_bit2_0[0] ;
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wire isr_int_prop_bit = isr_int_prop && icr_bit2_0[0] ;
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wire meta_isr_int_prop_bit ;
|
wire meta_isr_int_prop_bit ;
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// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
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// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
|
synchronizer_flop isr_bit0_sync
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synchronizer_flop #(1, 0) isr_bit0_sync
|
(
|
(
|
.data_in (isr_int_prop_bit),
|
.data_in (isr_int_prop_bit),
|
.clk_out (pci_clk),
|
.clk_out (pci_clk),
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.sync_data_out (meta_isr_int_prop_bit),
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.sync_data_out (meta_isr_int_prop_bit),
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.async_reset (reset)
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.async_reset (reset)
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| Line 3108... |
Line 3111... |
assign int_in = isr_int_prop_bit || isr_bit2_0[1] || isr_bit2_0[2] || isr_bit4_3[3] || isr_bit4_3[4];
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assign int_in = isr_int_prop_bit || isr_bit2_0[1] || isr_bit2_0[2] || isr_bit4_3[3] || isr_bit4_3[4];
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`else // not SYNCHRONEOUS_CLOCK_DOMAINS
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`else // not SYNCHRONEOUS_CLOCK_DOMAINS
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assign int_in = isr_int_prop_bit || isr_bit1 || isr_bit2_0[2] || isr_bits4_3[3] || isr_bits4_3[4];
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assign int_in = isr_int_prop_bit || isr_bit1 || isr_bit2_0[2] || isr_bits4_3[3] || isr_bits4_3[4];
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`endif
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`endif
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// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
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// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
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synchronizer_flop int_pin_sync
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synchronizer_flop #(1, 0) int_pin_sync
|
(
|
(
|
.data_in (int_in),
|
.data_in (int_in),
|
.clk_out (wb_clk),
|
.clk_out (wb_clk),
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.sync_data_out (int_meta),
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.sync_data_out (int_meta),
|
.async_reset (reset)
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.async_reset (reset)
|
| Line 3129... |
Line 3132... |
assign int_in = isr_int_prop_bit || isr_bit2_0[1] || isr_bit2_0[2];
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assign int_in = isr_int_prop_bit || isr_bit2_0[1] || isr_bit2_0[2];
|
`else // not SYNCHRONEOUS_CLOCK_DOMAINS
|
`else // not SYNCHRONEOUS_CLOCK_DOMAINS
|
assign int_in = isr_int_prop_bit || isr_bit2_0[1] || isr_bit2;
|
assign int_in = isr_int_prop_bit || isr_bit2_0[1] || isr_bit2;
|
`endif
|
`endif
|
// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
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// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
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synchronizer_flop int_pin_sync
|
synchronizer_flop #(1, 0) int_pin_sync
|
(
|
(
|
.data_in (int_in),
|
.data_in (int_in),
|
.clk_out (pci_clk),
|
.clk_out (pci_clk),
|
.sync_data_out (int_meta),
|
.sync_data_out (int_meta),
|
.async_reset (reset)
|
.async_reset (reset)
|
| Line 3154... |
Line 3157... |
// if bridge is HOST then write clock is equal to WB clock, and synchronization of outputs has to be done
|
// if bridge is HOST then write clock is equal to WB clock, and synchronization of outputs has to be done
|
`ifdef HOST
|
`ifdef HOST
|
wire [3:0] command_bits = {command_bit8, command_bit6, command_bit2_0[1:0]} ;
|
wire [3:0] command_bits = {command_bit8, command_bit6, command_bit2_0[1:0]} ;
|
wire [3:0] meta_command_bits ;
|
wire [3:0] meta_command_bits ;
|
reg [3:0] sync_command_bits ;
|
reg [3:0] sync_command_bits ;
|
synchronizer_flop #(4) command_bits_sync
|
synchronizer_flop #(4, 0) command_bits_sync
|
(
|
(
|
.data_in (command_bits),
|
.data_in (command_bits),
|
.clk_out (pci_clk),
|
.clk_out (pci_clk),
|
.sync_data_out (meta_command_bits),
|
.sync_data_out (meta_command_bits),
|
.async_reset (reset)
|
.async_reset (reset)
|
| Line 3177... |
Line 3180... |
wire sync_command_bit2 = command_bit2_0[2] ;
|
wire sync_command_bit2 = command_bit2_0[2] ;
|
`else // GUEST
|
`else // GUEST
|
wire command_bit = command_bit2_0[2] ;
|
wire command_bit = command_bit2_0[2] ;
|
wire meta_command_bit ;
|
wire meta_command_bit ;
|
reg sync_command_bit ;
|
reg sync_command_bit ;
|
synchronizer_flop command_bit_sync
|
synchronizer_flop #(1, 0) command_bit_sync
|
(
|
(
|
.data_in (command_bit),
|
.data_in (command_bit),
|
.clk_out (pci_clk),
|
.clk_out (pci_clk),
|
.sync_data_out (meta_command_bit),
|
.sync_data_out (meta_command_bit),
|
.async_reset (reset)
|
.async_reset (reset)
|
| Line 3213... |
Line 3216... |
(!cache_line_size_reg[1] && !cache_line_size_reg[0]) );
|
(!cache_line_size_reg[1] && !cache_line_size_reg[0]) );
|
`ifdef HOST
|
`ifdef HOST
|
wire [7:2] cache_lsize_to_pci_bits = { cache_line_size_reg[7:2] } ;
|
wire [7:2] cache_lsize_to_pci_bits = { cache_line_size_reg[7:2] } ;
|
wire [7:2] meta_cache_lsize_to_pci_bits ;
|
wire [7:2] meta_cache_lsize_to_pci_bits ;
|
reg [7:2] sync_cache_lsize_to_pci_bits ;
|
reg [7:2] sync_cache_lsize_to_pci_bits ;
|
synchronizer_flop #(6) cache_lsize_to_pci_bits_sync
|
synchronizer_flop #(6, 0) cache_lsize_to_pci_bits_sync
|
(
|
(
|
.data_in (cache_lsize_to_pci_bits),
|
.data_in (cache_lsize_to_pci_bits),
|
.clk_out (pci_clk),
|
.clk_out (pci_clk),
|
.sync_data_out (meta_cache_lsize_to_pci_bits),
|
.sync_data_out (meta_cache_lsize_to_pci_bits),
|
.async_reset (reset)
|
.async_reset (reset)
|
| Line 3234... |
Line 3237... |
wire sync_cache_lsize_not_zero_to_wb = cache_lsize_not_zero ;
|
wire sync_cache_lsize_not_zero_to_wb = cache_lsize_not_zero ;
|
// Latency timer is sinchronized only to PCI clock when bridge implementation is HOST
|
// Latency timer is sinchronized only to PCI clock when bridge implementation is HOST
|
wire [7:0] latency_timer_bits = latency_timer ;
|
wire [7:0] latency_timer_bits = latency_timer ;
|
wire [7:0] meta_latency_timer_bits ;
|
wire [7:0] meta_latency_timer_bits ;
|
reg [7:0] sync_latency_timer_bits ;
|
reg [7:0] sync_latency_timer_bits ;
|
synchronizer_flop #(8) latency_timer_bits_sync
|
synchronizer_flop #(8, 0) latency_timer_bits_sync
|
(
|
(
|
.data_in (latency_timer_bits),
|
.data_in (latency_timer_bits),
|
.clk_out (pci_clk),
|
.clk_out (pci_clk),
|
.sync_data_out (meta_latency_timer_bits),
|
.sync_data_out (meta_latency_timer_bits),
|
.async_reset (reset)
|
.async_reset (reset)
|
| Line 3253... |
Line 3256... |
wire [7:0] sync_latency_timer = sync_latency_timer_bits ;
|
wire [7:0] sync_latency_timer = sync_latency_timer_bits ;
|
`else // GUEST
|
`else // GUEST
|
wire [8:2] cache_lsize_to_wb_bits = { cache_lsize_not_zero, cache_line_size_reg[7:2] } ;
|
wire [8:2] cache_lsize_to_wb_bits = { cache_lsize_not_zero, cache_line_size_reg[7:2] } ;
|
wire [8:2] meta_cache_lsize_to_wb_bits ;
|
wire [8:2] meta_cache_lsize_to_wb_bits ;
|
reg [8:2] sync_cache_lsize_to_wb_bits ;
|
reg [8:2] sync_cache_lsize_to_wb_bits ;
|
synchronizer_flop #(7) cache_lsize_to_wb_bits_sync
|
synchronizer_flop #(7, 0) cache_lsize_to_wb_bits_sync
|
(
|
(
|
.data_in (cache_lsize_to_wb_bits),
|
.data_in (cache_lsize_to_wb_bits),
|
.clk_out (wb_clk),
|
.clk_out (wb_clk),
|
.sync_data_out (meta_cache_lsize_to_wb_bits),
|
.sync_data_out (meta_cache_lsize_to_wb_bits),
|
.async_reset (reset)
|
.async_reset (reset)
|
