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[/] [pci/] [tags/] [rel_7/] [rtl/] [verilog/] [pci_io_mux_ad_load_crit.v] - Diff between revs 18 and 77
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2002/02/01 14:43:31 mihad
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// *** empty log message ***
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//
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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// module is provided for last level of logic for loading AD output flip-flops
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// module is provided for last level of logic for loading AD output flip-flops
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// and output backup flip - flops
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// and output backup flip - flops
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module PCI_IO_MUX_AD_LOAD_CRIT
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module pci_io_mux_ad_load_crit
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(
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(
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load_in,
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load_in,
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load_on_transfer_in,
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load_on_transfer_in,
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pci_irdy_in,
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pci_irdy_in,
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pci_trdy_in,
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pci_trdy_in,
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output load_out ;
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output load_out ;
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assign load_out = load_in || (load_on_transfer_in && ~pci_irdy_in && ~pci_trdy_in) ;
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assign load_out = load_in || (load_on_transfer_in && ~pci_irdy_in && ~pci_trdy_in) ;
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endmodule
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endmodule
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