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[/] [pci/] [tags/] [rel_7/] [rtl/] [verilog/] [pci_par_crit.v] - Diff between revs 77 and 83
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2003/01/27 16:49:31 mihad
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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//
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// Revision 1.3 2002/02/01 15:25:12 mihad
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// Revision 1.3 2002/02/01 15:25:12 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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// Repaired a few bugs, updated specification, added test bench files and design document
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//
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//
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// Revision 1.2 2001/10/05 08:14:28 mihad
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// Revision 1.2 2001/10/05 08:14:28 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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// Updated all files with inclusion of timescale file for simulation purposes.
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pci_cbe_en_in,
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pci_cbe_en_in,
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data_par_in ;
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data_par_in ;
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input [3:0] pci_cbe_in ;
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input [3:0] pci_cbe_in ;
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assign par_out = pci_cbe_en_in ? par_out_in : ( pci_cbe_in[3] ^^ pci_cbe_in[2] ^^ pci_cbe_in[1] ^^ pci_cbe_in[0] ^^ data_par_in) ;
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assign par_out = pci_cbe_en_in ? par_out_in : ( pci_cbe_in[3] ^ pci_cbe_in[2] ^ pci_cbe_in[1] ^ pci_cbe_in[0] ^ data_par_in) ;
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endmodule
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endmodule
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