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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2003/01/27 16:49:31 mihad
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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//
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// Revision 1.4 2002/08/13 11:03:53 mihad
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// Revision 1.4 2002/08/13 11:03:53 mihad
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// Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image
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// Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image
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//
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//
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// Revision 1.3 2002/02/01 15:25:12 mihad
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// Revision 1.3 2002/02/01 15:25:12 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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// Repaired a few bugs, updated specification, added test bench files and design document
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reg check_perr ;
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reg check_perr ;
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/*=======================================================================================================================
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/*=======================================================================================================================
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CBE lines' parity is needed for overall parity calculation
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CBE lines' parity is needed for overall parity calculation
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=======================================================================================================================*/
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=======================================================================================================================*/
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wire par_cbe_out = pci_cbe_out_in[3] ^^ pci_cbe_out_in[2] ^^ pci_cbe_out_in[1] ^^ pci_cbe_out_in[0] ;
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wire par_cbe_out = pci_cbe_out_in[3] ^ pci_cbe_out_in[2] ^ pci_cbe_out_in[1] ^ pci_cbe_out_in[0] ;
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wire par_cbe_in = pci_cbe_reg_in[3] ^^ pci_cbe_reg_in[2] ^^ pci_cbe_reg_in[1] ^^ pci_cbe_reg_in[0] ;
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wire par_cbe_in = pci_cbe_reg_in[3] ^ pci_cbe_reg_in[2] ^ pci_cbe_reg_in[1] ^ pci_cbe_reg_in[0] ;
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/*=======================================================================================================================
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/*=======================================================================================================================
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Parity generator - parity is generated and assigned to output on every clock edge. PAR output enable is active
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Parity generator - parity is generated and assigned to output on every clock edge. PAR output enable is active
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one clock cycle after data output enable. Depending on whether master is performing access or target is responding,
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one clock cycle after data output enable. Depending on whether master is performing access or target is responding,
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apropriate cbe data is included in parity generation. Non - registered CBE is used during reads through target SM
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apropriate cbe data is included in parity generation. Non - registered CBE is used during reads through target SM
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=======================================================================================================================*/
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=======================================================================================================================*/
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// generate appropriate par signal
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// generate appropriate par signal
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wire data_par = (pci_ad_out_in[31] ^^ pci_ad_out_in[30] ^^ pci_ad_out_in[29] ^^ pci_ad_out_in[28]) ^^
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wire data_par = (pci_ad_out_in[31] ^ pci_ad_out_in[30] ^ pci_ad_out_in[29] ^ pci_ad_out_in[28]) ^
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(pci_ad_out_in[27] ^^ pci_ad_out_in[26] ^^ pci_ad_out_in[25] ^^ pci_ad_out_in[24]) ^^
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(pci_ad_out_in[27] ^ pci_ad_out_in[26] ^ pci_ad_out_in[25] ^ pci_ad_out_in[24]) ^
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(pci_ad_out_in[23] ^^ pci_ad_out_in[22] ^^ pci_ad_out_in[21] ^^ pci_ad_out_in[20]) ^^
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(pci_ad_out_in[23] ^ pci_ad_out_in[22] ^ pci_ad_out_in[21] ^ pci_ad_out_in[20]) ^
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(pci_ad_out_in[19] ^^ pci_ad_out_in[18] ^^ pci_ad_out_in[17] ^^ pci_ad_out_in[16]) ^^
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(pci_ad_out_in[19] ^ pci_ad_out_in[18] ^ pci_ad_out_in[17] ^ pci_ad_out_in[16]) ^
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(pci_ad_out_in[15] ^^ pci_ad_out_in[14] ^^ pci_ad_out_in[13] ^^ pci_ad_out_in[12]) ^^
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(pci_ad_out_in[15] ^ pci_ad_out_in[14] ^ pci_ad_out_in[13] ^ pci_ad_out_in[12]) ^
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(pci_ad_out_in[11] ^^ pci_ad_out_in[10] ^^ pci_ad_out_in[9] ^^ pci_ad_out_in[8]) ^^
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(pci_ad_out_in[11] ^ pci_ad_out_in[10] ^ pci_ad_out_in[9] ^ pci_ad_out_in[8]) ^
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(pci_ad_out_in[7] ^^ pci_ad_out_in[6] ^^ pci_ad_out_in[5] ^^ pci_ad_out_in[4]) ^^
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(pci_ad_out_in[7] ^ pci_ad_out_in[6] ^ pci_ad_out_in[5] ^ pci_ad_out_in[4]) ^
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(pci_ad_out_in[3] ^^ pci_ad_out_in[2] ^^ pci_ad_out_in[1] ^^ pci_ad_out_in[0]) ;
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(pci_ad_out_in[3] ^ pci_ad_out_in[2] ^ pci_ad_out_in[1] ^ pci_ad_out_in[0]) ;
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wire par_out_only = data_par ^^ par_cbe_out ;
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wire par_out_only = data_par ^ par_cbe_out ;
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pci_par_crit par_gen
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pci_par_crit par_gen
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(
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(
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.par_out (pci_par_out),
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.par_out (pci_par_out),
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.par_out_in (par_out_only),
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.par_out_in (par_out_only),
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// equation indicating whether to check and generate or not PERR# signal on next cycle
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// equation indicating whether to check and generate or not PERR# signal on next cycle
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wire perr_generate = ~pci_par_en_in && ~pci_ad_en_in // par was not generated on this cycle, so it should be checked
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wire perr_generate = ~pci_par_en_in && ~pci_ad_en_in // par was not generated on this cycle, so it should be checked
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&& ((pci_irdy_en_in && ~pci_trdy_reg_in) || // and master is driving irdy and target is signaling ready
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&& ((pci_irdy_en_in && ~pci_trdy_reg_in) || // and master is driving irdy and target is signaling ready
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(pci_trdy_en_in && ~pci_irdy_reg_in)) ; // or target is driving trdy and master is signaling ready
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(pci_trdy_en_in && ~pci_irdy_reg_in)) ; // or target is driving trdy and master is signaling ready
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wire data_in_par = (pci_ad_reg_in[31] ^^ pci_ad_reg_in[30] ^^ pci_ad_reg_in[29] ^^ pci_ad_reg_in[28]) ^^
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wire data_in_par = (pci_ad_reg_in[31] ^ pci_ad_reg_in[30] ^ pci_ad_reg_in[29] ^ pci_ad_reg_in[28]) ^
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(pci_ad_reg_in[27] ^^ pci_ad_reg_in[26] ^^ pci_ad_reg_in[25] ^^ pci_ad_reg_in[24]) ^^
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(pci_ad_reg_in[27] ^ pci_ad_reg_in[26] ^ pci_ad_reg_in[25] ^ pci_ad_reg_in[24]) ^
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(pci_ad_reg_in[23] ^^ pci_ad_reg_in[22] ^^ pci_ad_reg_in[21] ^^ pci_ad_reg_in[20]) ^^
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(pci_ad_reg_in[23] ^ pci_ad_reg_in[22] ^ pci_ad_reg_in[21] ^ pci_ad_reg_in[20]) ^
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(pci_ad_reg_in[19] ^^ pci_ad_reg_in[18] ^^ pci_ad_reg_in[17] ^^ pci_ad_reg_in[16]) ^^
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(pci_ad_reg_in[19] ^ pci_ad_reg_in[18] ^ pci_ad_reg_in[17] ^ pci_ad_reg_in[16]) ^
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(pci_ad_reg_in[15] ^^ pci_ad_reg_in[14] ^^ pci_ad_reg_in[13] ^^ pci_ad_reg_in[12]) ^^
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(pci_ad_reg_in[15] ^ pci_ad_reg_in[14] ^ pci_ad_reg_in[13] ^ pci_ad_reg_in[12]) ^
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(pci_ad_reg_in[11] ^^ pci_ad_reg_in[10] ^^ pci_ad_reg_in[9] ^^ pci_ad_reg_in[8]) ^^
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(pci_ad_reg_in[11] ^ pci_ad_reg_in[10] ^ pci_ad_reg_in[9] ^ pci_ad_reg_in[8]) ^
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(pci_ad_reg_in[7] ^^ pci_ad_reg_in[6] ^^ pci_ad_reg_in[5] ^^ pci_ad_reg_in[4]) ^^
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(pci_ad_reg_in[7] ^ pci_ad_reg_in[6] ^ pci_ad_reg_in[5] ^ pci_ad_reg_in[4]) ^
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(pci_ad_reg_in[3] ^^ pci_ad_reg_in[2] ^^ pci_ad_reg_in[1] ^^ pci_ad_reg_in[0]) ;
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(pci_ad_reg_in[3] ^ pci_ad_reg_in[2] ^ pci_ad_reg_in[1] ^ pci_ad_reg_in[0]) ;
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//wire perr = (cbe_par_reg ^ pci_par_in ^ data_in_par) ;
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//wire perr = (cbe_par_reg ^ pci_par_in ^ data_in_par) ;
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wire perr ;
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wire perr ;
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wire perr_n ;
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wire perr_n ;
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wire perr_en ;
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wire perr_en ;
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assign pci_perr_out = perr_n ;
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assign pci_perr_out = perr_n ;
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// parity error output assignment
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// parity error output assignment
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//assign pci_perr_out = ~(perr && perr_generate) ;
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//assign pci_perr_out = ~(perr && perr_generate) ;
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wire non_critical_par = par_cbe_in ^^ data_in_par ;
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wire non_critical_par = par_cbe_in ^ data_in_par ;
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pci_perr_crit perr_crit_gen
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pci_perr_crit perr_crit_gen
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(
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(
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.perr_out (perr),
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.perr_out (perr),
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.perr_n_out (perr_n),
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.perr_n_out (perr_n),
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