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Line 40... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2003/07/29 08:20:11 mihad
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// Found and simulated the problem in the synchronization logic.
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// Repaired the synchronization logic in the FIFOs.
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//
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//
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//
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/* FIFO_CONTROL module provides read/write address and status generation for
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/* FIFO_CONTROL module provides read/write address and status generation for
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FIFOs implemented with standard dual port SRAM cells in ASIC or FPGA designs */
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FIFOs implemented with standard dual port SRAM cells in ASIC or FPGA designs */
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`include "pci_constants.v"
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`include "pci_constants.v"
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Line 68... |
empty_out,
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empty_out,
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waddr_out,
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waddr_out,
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raddr_out,
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raddr_out,
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rallow_out,
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rallow_out,
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wallow_out,
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wallow_out,
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three_left_out,
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two_left_out
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two_left_out
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);
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);
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parameter ADDR_LENGTH = 7 ;
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parameter ADDR_LENGTH = 7 ;
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Line 96... |
output [(ADDR_LENGTH - 1):0] waddr_out, raddr_out;
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output [(ADDR_LENGTH - 1):0] waddr_out, raddr_out;
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// read and write allow outputs
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// read and write allow outputs
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output rallow_out, wallow_out ;
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output rallow_out, wallow_out ;
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// two locations left output indicator
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// three and two locations left output indicator
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output three_left_out ;
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output two_left_out ;
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output two_left_out ;
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// read address register
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// read address register
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reg [(ADDR_LENGTH - 1):0] raddr ;
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reg [(ADDR_LENGTH - 1):0] raddr ;
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// write address register
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// write address register
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reg [(ADDR_LENGTH - 1):0] waddr;
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reg [(ADDR_LENGTH - 1):0] waddr;
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reg [(ADDR_LENGTH - 1):0] waddr_plus1;
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assign waddr_out = waddr ;
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assign waddr_out = waddr ;
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// grey code registers
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// grey code registers
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// grey code pipeline for write address
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// grey code pipeline for write address
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reg [(ADDR_LENGTH - 1):0] wgrey_minus1 ; // previous
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reg [(ADDR_LENGTH - 1):0] wgrey_minus1 ; // previous
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reg [(ADDR_LENGTH - 1):0] wgrey_addr ; // current
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reg [(ADDR_LENGTH - 1):0] wgrey_addr ; // current
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reg [(ADDR_LENGTH - 1):0] wgrey_next ; // next
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reg [(ADDR_LENGTH - 1):0] wgrey_next ; // next
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reg [(ADDR_LENGTH - 1):0] wgrey_next_plus1 ; // next plus 1
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// next write gray address calculation - bitwise xor between address and shifted address
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// next write gray address calculation - bitwise xor between address and shifted address
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wire [(ADDR_LENGTH - 2):0] calc_wgrey_next = waddr[(ADDR_LENGTH - 1):1] ^ waddr[(ADDR_LENGTH - 2):0] ;
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wire [(ADDR_LENGTH - 2):0] calc_wgrey_next = waddr[(ADDR_LENGTH - 1):1] ^ waddr[(ADDR_LENGTH - 2):0] ;
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wire [(ADDR_LENGTH - 2):0] calc_wgrey_next_plus1 = waddr_plus1[(ADDR_LENGTH - 1):1] ^ waddr_plus1[(ADDR_LENGTH - 2):0] ;
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// grey code pipeline for read address
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// grey code pipeline for read address
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reg [(ADDR_LENGTH - 1):0] rgrey_minus2 ; // two before current
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reg [(ADDR_LENGTH - 1):0] rgrey_minus2 ; // two before current
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reg [(ADDR_LENGTH - 1):0] rgrey_minus1 ; // one before current
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reg [(ADDR_LENGTH - 1):0] rgrey_minus1 ; // one before current
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reg [(ADDR_LENGTH - 1):0] rgrey_addr ; // current
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reg [(ADDR_LENGTH - 1):0] rgrey_addr ; // current
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if (clear)
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if (clear)
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begin
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begin
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// initial values seem a bit odd - they are this way to allow easier grey pipeline implementation and to allow min fifo size of 8
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// initial values seem a bit odd - they are this way to allow easier grey pipeline implementation and to allow min fifo size of 8
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raddr_plus_one <= #`FF_DELAY 5 ;
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raddr_plus_one <= #`FF_DELAY 5 ;
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raddr <= #`FF_DELAY 4 ;
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raddr <= #`FF_DELAY 4 ;
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// raddr_plus_one <= #`FF_DELAY 6 ;
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// raddr <= #`FF_DELAY 5 ;
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end
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end
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else if (rallow_out)
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else if (rallow_out)
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begin
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begin
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raddr_plus_one <= #`FF_DELAY raddr_plus_one + 1'b1 ;
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raddr_plus_one <= #`FF_DELAY raddr_plus_one + 1'b1 ;
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raddr <= #`FF_DELAY raddr_plus_one ;
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raddr <= #`FF_DELAY raddr_plus_one ;
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Line 197... |
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/*--------------------------------------------------------------------------------------------
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/*--------------------------------------------------------------------------------------------
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Write address control consists of write address counter and 3 Grey Code Registers:
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Write address control consists of write address counter and 3 Grey Code Registers:
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- wgrey_minus1 represents previous Grey coded write address
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- wgrey_minus1 represents previous Grey coded write address
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- wgrey_addr represents current Grey Coded write address
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- wgrey_addr represents current Grey Coded write address
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- wgrey_next represents Grey Coded next write address
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- wgrey_next represents next Grey Coded write address
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- wgrey_next_plus1 represents second next Grey Coded write address
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----------------------------------------------------------------------------------------------*/
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----------------------------------------------------------------------------------------------*/
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// grey coded address pipeline for status generation in write clock domain
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// grey coded address pipeline for status generation in write clock domain
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always@(posedge wclock_in or posedge clear)
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always@(posedge wclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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begin
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begin
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wgrey_minus1 <= #`FF_DELAY 1 ;
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wgrey_minus1 <= #`FF_DELAY 1 ;
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wgrey_addr <= #1 3 ;
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wgrey_addr <= #`FF_DELAY 3 ;
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wgrey_next <= #`FF_DELAY 2 ;
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wgrey_next <= #`FF_DELAY 2 ;
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wgrey_next_plus1 <= #`FF_DELAY 6;
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end
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end
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else
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else
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if (wallow_out)
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if (wallow_out)
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begin
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begin
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wgrey_minus1 <= #`FF_DELAY wgrey_addr ;
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wgrey_minus1 <= #`FF_DELAY wgrey_addr ;
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wgrey_addr <= #1 wgrey_next ;
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wgrey_addr <= #`FF_DELAY wgrey_next ;
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wgrey_next <= #`FF_DELAY {waddr[(ADDR_LENGTH - 1)], calc_wgrey_next} ;
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wgrey_next <= #`FF_DELAY {waddr[(ADDR_LENGTH - 1)], calc_wgrey_next} ;
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// wgrey_next <= #`FF_DELAY wgrey_next_plus1 ;
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wgrey_next_plus1 <= #`FF_DELAY {waddr_plus1[(ADDR_LENGTH - 1)], calc_wgrey_next_plus1} ;
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end
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end
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end
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end
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// write address counter - nothing special except initial value
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// write address counter - nothing special except initial value
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always@(posedge wclock_in or posedge clear)
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always@(posedge wclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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begin
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// initial value 5
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// initial value 5
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waddr <= #`FF_DELAY 4 ;
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waddr <= #`FF_DELAY 4 ;
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waddr_plus1 <= #`FF_DELAY 5 ;
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end
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else
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else
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if (wallow_out)
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if (wallow_out)
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begin
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waddr <= #`FF_DELAY waddr + 1'b1 ;
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waddr <= #`FF_DELAY waddr + 1'b1 ;
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waddr_plus1 <= #`FF_DELAY waddr_plus1 + 1'b1 ;
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end
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end
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end
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/*------------------------------------------------------------------------------------------------------------------------------
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/*------------------------------------------------------------------------------------------------------------------------------
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Gray coded address of read address decremented by two is synchronized to write clock domain and compared to:
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Gray coded address of read address decremented by two is synchronized to write clock domain and compared to:
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- previous grey coded write address - if they are equal, the fifo is full
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- previous grey coded write address - if they are equal, the fifo is full
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Line 280... |
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assign full_out = (wgrey_minus1 == wclk_rgrey_minus2) ;
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assign full_out = (wgrey_minus1 == wclk_rgrey_minus2) ;
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assign almost_full_out = (wgrey_addr == wclk_rgrey_minus2) ;
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assign almost_full_out = (wgrey_addr == wclk_rgrey_minus2) ;
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assign two_left_out = (wgrey_next == wclk_rgrey_minus2) ;
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assign two_left_out = (wgrey_next == wclk_rgrey_minus2) ;
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assign three_left_out = (wgrey_next_plus1 == wclk_rgrey_minus2) ;
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/*------------------------------------------------------------------------------------------------------------------------------
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/*------------------------------------------------------------------------------------------------------------------------------
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Empty control:
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Empty control:
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Gray coded write address pointer is synchronized to read clock domain and compared to Gray coded read address pointer.
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Gray coded write address pointer is synchronized to read clock domain and compared to Gray coded read address pointer.
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If they are equal, fifo is empty.
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If they are equal, fifo is empty.
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