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Line 40... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2003/08/08 16:36:33 tadejm
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// Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure.
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//
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// Revision 1.3 2003/07/29 08:20:11 mihad
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// Revision 1.3 2003/07/29 08:20:11 mihad
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// Found and simulated the problem in the synchronization logic.
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// Found and simulated the problem in the synchronization logic.
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// Repaired the synchronization logic in the FIFOs.
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// Repaired the synchronization logic in the FIFOs.
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//
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//
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//
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//
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Line 259... |
- grey coded next write address. If they are equal, the fifo has two free locations left.
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- grey coded next write address. If they are equal, the fifo has two free locations left.
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--------------------------------------------------------------------------------------------------------------------------------*/
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--------------------------------------------------------------------------------------------------------------------------------*/
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wire [(ADDR_LENGTH - 1):0] wclk_sync_rgrey_minus2 ;
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wire [(ADDR_LENGTH - 1):0] wclk_sync_rgrey_minus2 ;
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reg [(ADDR_LENGTH - 1):0] wclk_rgrey_minus2 ;
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reg [(ADDR_LENGTH - 1):0] wclk_rgrey_minus2 ;
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synchronizer_flop #(ADDR_LENGTH, 0) i_synchronizer_reg_rgrey_minus2
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pci_synchronizer_flop #(ADDR_LENGTH, 0) i_synchronizer_reg_rgrey_minus2
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(
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(
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.data_in (rgrey_minus2),
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.data_in (rgrey_minus2),
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.clk_out (wclock_in),
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.clk_out (wclock_in),
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.sync_data_out (wclk_sync_rgrey_minus2),
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.sync_data_out (wclk_sync_rgrey_minus2),
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.async_reset (clear)
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.async_reset (clear)
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Line 297... |
Synchronized write pointer is also compared to Gray coded next read address. If these two are
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Synchronized write pointer is also compared to Gray coded next read address. If these two are
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equal, fifo is almost empty.
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equal, fifo is almost empty.
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--------------------------------------------------------------------------------------------------------------------------------*/
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--------------------------------------------------------------------------------------------------------------------------------*/
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wire [(ADDR_LENGTH - 1):0] rclk_sync_wgrey_addr ;
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wire [(ADDR_LENGTH - 1):0] rclk_sync_wgrey_addr ;
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reg [(ADDR_LENGTH - 1):0] rclk_wgrey_addr ;
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reg [(ADDR_LENGTH - 1):0] rclk_wgrey_addr ;
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synchronizer_flop #(ADDR_LENGTH, 3) i_synchronizer_reg_wgrey_addr
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pci_synchronizer_flop #(ADDR_LENGTH, 3) i_synchronizer_reg_wgrey_addr
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(
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(
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.data_in (wgrey_addr),
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.data_in (wgrey_addr),
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.clk_out (rclock_in),
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.clk_out (rclock_in),
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.sync_data_out (rclk_sync_wgrey_addr),
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.sync_data_out (rclk_sync_wgrey_addr),
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.async_reset (clear)
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.async_reset (clear)
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