URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_7/] [rtl/] [verilog/] [pci_rst_int.v] - Diff between revs 18 and 77

Rev 18	Rev 77
Line 40...	Line 40...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.1 2002/02/01 14:43:31 mihad`
	`// * empty log message *`
	`//`
`//`	`//`
`//`	`//`

`include "pci_constants.v"	`include "pci_constants.v"

`// synopsys translate_off`	`// synopsys translate_off`
`include "timescale.v"	`include "timescale.v"
`// synopsys translate_on`	`// synopsys translate_on`

`// Module is used to switch appropriate reset and interrupt signals with few logic`	`// Module is used to switch appropriate reset and interrupt signals with few logic`
`module PCI_RST_INT`	`module pci_rst_int`
`(`	`(`
`clk_in,`	`clk_in,`
`// reset signals`	`// reset signals`
`rst_i,`	`rst_i,`
`pci_rstn_in,`	`pci_rstn_in,`
Line 137...	Line 140...
`endif	`endif
`else	`else
`// guest implementation of the bridge gets its interrupt from WISHBONE bus - INT_I and propagates it to PCI bus`	`// guest implementation of the bridge gets its interrupt from WISHBONE bus - INT_I and propagates it to PCI bus`
`ifdef GUEST	`ifdef GUEST
`wire interrupt_a_en;`	`wire interrupt_a_en;`
`OUT_REG inta`	`pci_out_reg inta`
`(`	`(`
`.reset_in ( reset ),`	`.reset_in ( reset ),`
`.clk_in ( clk_in) ,`	`.clk_in ( clk_in) ,`
`.dat_en_in ( 1'b1 ),`	`.dat_en_in ( 1'b1 ),`
`.en_en_in ( 1'b1 ),`	`.en_en_in ( 1'b1 ),`