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[/] [pci/] [tags/] [rel_7/] [rtl/] [verilog/] [pci_target32_clk_en.v] - Diff between revs 21 and 77
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Rev 77 |
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/02/01 15:25:12 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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//
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// Revision 1.2 2001/10/05 08:14:30 mihad
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// Revision 1.2 2001/10/05 08:14:30 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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//
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// New project directory structure
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// New project directory structure
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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module PCI_TARGET32_CLK_EN
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module pci_target32_clk_en
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(
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(
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addr_phase,
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addr_phase,
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config_access,
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config_access,
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addr_claim_in,
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addr_claim_in,
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pci_frame_in,
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pci_frame_in,
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// Clock enable signal for FSM with preserved hierarchy for minimum delay!
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// Clock enable signal for FSM with preserved hierarchy for minimum delay!
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assign clk_enable = (s_idle_clk_en || s_wait_clk_en || s_tran_clk_en) ;
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assign clk_enable = (s_idle_clk_en || s_wait_clk_en || s_tran_clk_en) ;
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endmodule
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endmodule
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