| Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.2 2001/10/05 08:14:30 mihad
|
|
// Updated all files with inclusion of timescale file for simulation purposes.
|
|
//
|
// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
|
// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
|
// New project directory structure
|
// New project directory structure
|
//
|
//
|
//
|
//
|
|
|
`include "bus_commands.v"
|
`include "bus_commands.v"
|
`include "constants.v"
|
`include "pci_constants.v"
|
|
|
|
// synopsys translate_off
|
`include "timescale.v"
|
`include "timescale.v"
|
|
// synopsys translate_on
|
|
|
module PCI_TARGET32_INTERFACE
|
module PCI_TARGET32_INTERFACE
|
(
|
(
|
// system inputs
|
// system inputs
|
clk_in,
|
clk_in,
|
| Line 66... |
Line 72... |
data_out,
|
data_out,
|
be_in,
|
be_in,
|
req_in,
|
req_in,
|
rdy_in,
|
rdy_in,
|
addr_phase_in,
|
addr_phase_in,
|
|
bckp_devsel_in,
|
bckp_trdy_in,
|
bckp_trdy_in,
|
|
bckp_stop_in,
|
last_reg_in,
|
last_reg_in,
|
frame_reg_in,
|
frame_reg_in,
|
fetch_pcir_fifo_in,
|
fetch_pcir_fifo_in,
|
load_medium_reg_in,
|
load_medium_reg_in,
|
sel_fifo_mreg_in,
|
sel_fifo_mreg_in,
|
| Line 83... |
Line 91... |
norm_access_to_config_out,
|
norm_access_to_config_out,
|
read_completed_out,
|
read_completed_out,
|
read_processing_out,
|
read_processing_out,
|
target_abort_out,
|
target_abort_out,
|
disconect_wo_data_out,
|
disconect_wo_data_out,
|
|
disconect_w_data_out,
|
pciw_fifo_full_out,
|
pciw_fifo_full_out,
|
pcir_fifo_data_err_out,
|
pcir_fifo_data_err_out,
|
wbw_fifo_empty_out,
|
wbw_fifo_empty_out,
|
|
wbu_del_read_comp_pending_out,
|
|
|
// Delayed synchronizacion module signals
|
// Delayed synchronizacion module signals
|
req_out,
|
req_out,
|
done_out,
|
done_out,
|
in_progress_out,
|
in_progress_out,
|
| Line 97... |
Line 107... |
req_comp_pending_in,
|
req_comp_pending_in,
|
addr_out,
|
addr_out,
|
be_out,
|
be_out,
|
we_out,
|
we_out,
|
bc_out,
|
bc_out,
|
burst_out,
|
burst_ok_out,
|
strd_addr_in,
|
strd_addr_in,
|
strd_bc_in,
|
strd_bc_in,
|
status_in,
|
status_in,
|
comp_flush_in,
|
comp_flush_in,
|
|
|
| Line 119... |
Line 129... |
pciw_fifo_control_out,
|
pciw_fifo_control_out,
|
pciw_fifo_two_left_in,
|
pciw_fifo_two_left_in,
|
pciw_fifo_almost_full_in,
|
pciw_fifo_almost_full_in,
|
pciw_fifo_full_in,
|
pciw_fifo_full_in,
|
wbw_fifo_empty_in,
|
wbw_fifo_empty_in,
|
|
wbu_del_read_comp_pending_in,
|
|
|
// Configuration space signals
|
// Configuration space signals
|
conf_hit_out,
|
conf_hit_out,
|
conf_addr_out,
|
conf_addr_out,
|
conf_data_out,
|
conf_data_out,
|
| Line 191... |
Line 202... |
input [3:0] be_in ; // current dataphase byte enable inputs - registered
|
input [3:0] be_in ; // current dataphase byte enable inputs - registered
|
// Port connection control signals from PCI FSM
|
// Port connection control signals from PCI FSM
|
input req_in ; // Read is requested to WB master from PCI side
|
input req_in ; // Read is requested to WB master from PCI side
|
input rdy_in ; // DATA / ADDRESS selection from PCI side when read or write - registered
|
input rdy_in ; // DATA / ADDRESS selection from PCI side when read or write - registered
|
input addr_phase_in ; // Indicates address phase and also fast-back-to-back address phase - registered
|
input addr_phase_in ; // Indicates address phase and also fast-back-to-back address phase - registered
|
input bckp_trdy_in ; // TRDY output (which is registered) equivalent
|
input bckp_devsel_in ; // DEVSEL input (which is registered) equivalent
|
|
input bckp_trdy_in ; // TRDY input (which is registered) equivalent
|
|
input bckp_stop_in ; // STOP input (which is registered) equivalent
|
input last_reg_in ; // Indicates last data phase - registered
|
input last_reg_in ; // Indicates last data phase - registered
|
input frame_reg_in ; // FRAME input signal - registered
|
input frame_reg_in ; // FRAME input signal - registered
|
input fetch_pcir_fifo_in ;// Read enable for PCIR_FIFO when when read is finishen on WB side
|
input fetch_pcir_fifo_in ;// Read enable for PCIR_FIFO when when read is finishen on WB side
|
input load_medium_reg_in ;// Load data from PCIR_FIFO to medium register (first data must be prepared on time)
|
input load_medium_reg_in ;// Load data from PCIR_FIFO to medium register (first data must be prepared on time)
|
input sel_fifo_mreg_in ; // Read data selection between PCIR_FIFO and medium register
|
input sel_fifo_mreg_in ; // Read data selection between PCIR_FIFO and medium register
|
| Line 211... |
Line 224... |
output same_read_out ; // Indicates the same read request (important when read is finished on WB side)
|
output same_read_out ; // Indicates the same read request (important when read is finished on WB side)
|
output norm_access_to_config_out ; // Indicates the access to Configuration space with MEMORY commands
|
output norm_access_to_config_out ; // Indicates the access to Configuration space with MEMORY commands
|
output read_completed_out ; // Indicates that read request is completed on WB side
|
output read_completed_out ; // Indicates that read request is completed on WB side
|
output read_processing_out ; // Indicates that read request is processing on WB side
|
output read_processing_out ; // Indicates that read request is processing on WB side
|
output target_abort_out ; // Indicates target abort termination
|
output target_abort_out ; // Indicates target abort termination
|
output disconect_wo_data_out ; // Indicates disconnect with OR without data termination
|
output disconect_wo_data_out ; // Indicates disconnect without data termination
|
|
output disconect_w_data_out ; // Indicates disconnect with data termination
|
output pciw_fifo_full_out ; // Indicates that write PCIW_FIFO is full
|
output pciw_fifo_full_out ; // Indicates that write PCIW_FIFO is full
|
output pcir_fifo_data_err_out ; // Indicates data error on current data read from PCIR_FIFO
|
output pcir_fifo_data_err_out ; // Indicates data error on current data read from PCIR_FIFO
|
output wbw_fifo_empty_out ; // Indicates that WB SLAVE has no data to be written to PCI bus
|
output wbw_fifo_empty_out ; // Indicates that WB SLAVE has no data to be written to PCI bus
|
|
output wbu_del_read_comp_pending_out ; // Indicates that WB Unit has a delayed read poending!
|
|
|
/*==================================================================================================================
|
/*==================================================================================================================
|
Read request interface through Delayed sinchronization module to WB Master
|
Read request interface through Delayed sinchronization module to WB Master
|
==================================================================================================================*/
|
==================================================================================================================*/
|
// request, completion, done and progress indicator outputs for delayed_sync module where they are synchronized
|
// request, completion, done and progress indicator outputs for delayed_sync module where they are synchronized
|
| Line 234... |
Line 248... |
// various data outputs - PCI Target sets address, bus command, byte enables, write enable and burst
|
// various data outputs - PCI Target sets address, bus command, byte enables, write enable and burst
|
output [31:0] addr_out ; // address bus output
|
output [31:0] addr_out ; // address bus output
|
output [3:0] be_out ; // byte enable output
|
output [3:0] be_out ; // byte enable output
|
output we_out ; // write enable output - read/write request indication 1 = write request / 0 = read request
|
output we_out ; // write enable output - read/write request indication 1 = write request / 0 = read request
|
output [3:0] bc_out ; // bus command output
|
output [3:0] bc_out ; // bus command output
|
output burst_out ; // pre-fetch enable & burst read - qualifies pre-fetch for access to current image space
|
output burst_ok_out ; // pre-fetch enable & burst read - qualifies pre-fetch for access to current image space
|
|
|
// completion side signals encoded termination status - 0 = normal completion / 1 = error terminated completion
|
// completion side signals encoded termination status - 0 = normal completion / 1 = error terminated completion
|
input [31:0] strd_addr_in ; // Stored requested read access address
|
input [31:0] strd_addr_in ; // Stored requested read access address
|
input [3:0] strd_bc_in ; // Stored requested read access bus command
|
input [3:0] strd_bc_in ; // Stored requested read access bus command
|
input status_in ; // Error status reported - NOT USED because FIFO control bits determin data error status
|
input status_in ; // Error status reported - NOT USED because FIFO control bits determin data error status
|
| Line 266... |
Line 280... |
input pciw_fifo_almost_full_in ; // almost full indicator from PCIW_FIFO
|
input pciw_fifo_almost_full_in ; // almost full indicator from PCIW_FIFO
|
input pciw_fifo_full_in ; // full indicator from PCIW_FIFO
|
input pciw_fifo_full_in ; // full indicator from PCIW_FIFO
|
|
|
// WBW_FIFO empy control signal used when delayed read is complete in PCIR_FIFO
|
// WBW_FIFO empy control signal used when delayed read is complete in PCIR_FIFO
|
input wbw_fifo_empty_in ; // empty indicator from WBW_FIFO
|
input wbw_fifo_empty_in ; // empty indicator from WBW_FIFO
|
|
input wbu_del_read_comp_pending_in ; // delayed read pending indicator from WB Unit
|
|
|
|
|
/*==================================================================================================================
|
/*==================================================================================================================
|
Configuration space signals - from and to registers
|
Configuration space signals - from and to registers
|
==================================================================================================================*/
|
==================================================================================================================*/
|
| Line 335... |
Line 350... |
reg [31:0] address ;
|
reg [31:0] address ;
|
// prefetch enable for access to selected image space
|
// prefetch enable for access to selected image space
|
reg pre_fetch_en ;
|
reg pre_fetch_en ;
|
|
|
// Input addresses and image hits from address decoders - addresses are multiplexed to address
|
// Input addresses and image hits from address decoders - addresses are multiplexed to address
|
|
`ifdef HOST
|
|
`ifdef NO_CNF_IMAGE
|
|
`ifdef PCI_IMAGE0 // if PCI bridge is HOST and IMAGE0 is assigned as general image space
|
|
wire hit0_in ;
|
|
wire [31:0] address0_in ;
|
|
wire pre_fetch_en0 = pre_fetch_en0_in ;
|
|
`else
|
|
wire hit0_in = 1'b0 ;
|
|
wire [31:0] address0_in = 32'h0 ;
|
|
wire pre_fetch_en0 = 1'b0 ;
|
|
`endif
|
|
`else
|
wire hit0_in ;
|
wire hit0_in ;
|
wire [31:0] address0_in ;
|
wire [31:0] address0_in ;
|
|
wire pre_fetch_en0 = pre_fetch_en0_in ;
|
|
`endif
|
|
`else // GUEST
|
|
wire hit0_in ;
|
|
wire [31:0] address0_in ;
|
|
wire pre_fetch_en0 = pre_fetch_en0_in ;
|
|
`endif
|
|
|
wire hit1_in ;
|
wire hit1_in ;
|
wire [31:0] address1_in ;
|
wire [31:0] address1_in ;
|
|
wire pre_fetch_en1 = pre_fetch_en1_in ;
|
|
|
`ifdef PCI_IMAGE2
|
`ifdef PCI_IMAGE2
|
wire hit2_in ;
|
wire hit2_in ;
|
wire [31:0] address2_in ;
|
wire [31:0] address2_in ;
|
|
wire pre_fetch_en2 = pre_fetch_en2_in ;
|
|
`else
|
|
wire hit2_in = 1'b0 ;
|
|
wire [31:0] address2_in = 32'h0 ;
|
|
wire pre_fetch_en2 = 1'b0 ;
|
`endif
|
`endif
|
|
|
`ifdef PCI_IMAGE3
|
`ifdef PCI_IMAGE3
|
wire hit2_in ;
|
|
wire [31:0] address2_in ;
|
|
wire hit3_in ;
|
wire hit3_in ;
|
wire [31:0] address3_in ;
|
wire [31:0] address3_in ;
|
|
wire pre_fetch_en3 = pre_fetch_en3_in ;
|
|
`else
|
|
wire hit3_in = 1'b0 ;
|
|
wire [31:0] address3_in = 32'h0 ;
|
|
wire pre_fetch_en3 = 1'b0 ;
|
`endif
|
`endif
|
|
|
`ifdef PCI_IMAGE4
|
`ifdef PCI_IMAGE4
|
wire hit2_in ;
|
|
wire [31:0] address2_in ;
|
|
wire hit3_in ;
|
|
wire [31:0] address3_in ;
|
|
wire hit4_in ;
|
wire hit4_in ;
|
wire [31:0] address4_in ;
|
wire [31:0] address4_in ;
|
|
wire pre_fetch_en4 = pre_fetch_en4_in ;
|
|
`else
|
|
wire hit4_in = 1'b0 ;
|
|
wire [31:0] address4_in = 32'h0 ;
|
|
wire pre_fetch_en4 = 1'b0 ;
|
`endif
|
`endif
|
|
|
`ifdef PCI_IMAGE5
|
`ifdef PCI_IMAGE5
|
wire hit2_in ;
|
|
wire [31:0] address2_in ;
|
|
wire hit3_in ;
|
|
wire [31:0] address3_in ;
|
|
wire hit4_in ;
|
|
wire [31:0] address4_in ;
|
|
wire hit5_in ;
|
|
wire [31:0] address5_in ;
|
|
`endif
|
|
`ifdef PCI_IMAGE6
|
|
wire hit2_in ;
|
|
wire [31:0] address2_in ;
|
|
wire hit3_in ;
|
|
wire [31:0] address3_in ;
|
|
wire hit4_in ;
|
|
wire [31:0] address4_in ;
|
|
wire hit5_in ;
|
wire hit5_in ;
|
wire [31:0] address5_in ;
|
wire [31:0] address5_in ;
|
|
wire pre_fetch_en5 = pre_fetch_en5_in ;
|
|
`else
|
|
wire hit5_in = 1'b0 ;
|
|
wire [31:0] address5_in = 32'h0 ;
|
|
wire pre_fetch_en5 = 1'b0 ;
|
`endif
|
`endif
|
|
|
// Include address decoders
|
// Include address decoders
|
|
`ifdef HOST
|
|
`ifdef NO_CNF_IMAGE
|
|
`ifdef PCI_IMAGE0 // if PCI bridge is HOST and IMAGE0 is assigned as general image space
|
|
PCI_DECODER #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder0
|
|
(.hit (hit0_in),
|
|
.addr_out (address0_in),
|
|
.addr_in (address_in),
|
|
.bc_in (bc_in),
|
|
.base_addr (pci_base_addr0_in),
|
|
.mask_addr (pci_addr_mask0_in),
|
|
.tran_addr (pci_tran_addr0_in),
|
|
.at_en (addr_tran_en0_in),
|
|
.mem_io_space (mem_io_addr_space0_in),
|
|
.mem_en (mem_enable_in),
|
|
.io_en (io_enable_in)
|
|
) ;
|
|
`endif
|
|
`else
|
PCI_DECODER #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder0
|
PCI_DECODER #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder0
|
(.hit (hit0_in),
|
(.hit (hit0_in),
|
.addr_out (address0_in),
|
.addr_out (address0_in),
|
.addr_in (address_in),
|
.addr_in (address_in),
|
|
.bc_in (bc_in),
|
.base_addr (pci_base_addr0_in),
|
.base_addr (pci_base_addr0_in),
|
.mask_addr (pci_addr_mask0_in),
|
.mask_addr (pci_addr_mask0_in),
|
.tran_addr (pci_tran_addr0_in),
|
.tran_addr (pci_tran_addr0_in),
|
.at_en (addr_tran_en0_in),
|
.at_en (addr_tran_en0_in),
|
.mem_io_space (mem_io_addr_space0_in),
|
.mem_io_space (mem_io_addr_space0_in),
|
.mem_en (mem_enable_in),
|
.mem_en (mem_enable_in),
|
.io_en (io_enable_in)
|
.io_en (io_enable_in)
|
) ;
|
) ;
|
|
`endif
|
|
`else // GUEST
|
|
PCI_DECODER #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder0
|
|
(.hit (hit0_in),
|
|
.addr_out (address0_in),
|
|
.addr_in (address_in),
|
|
.bc_in (bc_in),
|
|
.base_addr (pci_base_addr0_in),
|
|
.mask_addr (pci_addr_mask0_in),
|
|
.tran_addr (pci_tran_addr0_in),
|
|
.at_en (addr_tran_en0_in),
|
|
.mem_io_space (mem_io_addr_space0_in),
|
|
.mem_en (mem_enable_in),
|
|
.io_en (io_enable_in)
|
|
) ;
|
|
`endif
|
PCI_DECODER #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder1
|
PCI_DECODER #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder1
|
(.hit (hit1_in),
|
(.hit (hit1_in),
|
.addr_out (address1_in),
|
.addr_out (address1_in),
|
.addr_in (address_in),
|
.addr_in (address_in),
|
|
.bc_in (bc_in),
|
.base_addr (pci_base_addr1_in),
|
.base_addr (pci_base_addr1_in),
|
.mask_addr (pci_addr_mask1_in),
|
.mask_addr (pci_addr_mask1_in),
|
.tran_addr (pci_tran_addr1_in),
|
.tran_addr (pci_tran_addr1_in),
|
.at_en (addr_tran_en1_in),
|
.at_en (addr_tran_en1_in),
|
.mem_io_space (mem_io_addr_space1_in),
|
.mem_io_space (mem_io_addr_space1_in),
|
| Line 408... |
Line 482... |
`ifdef PCI_IMAGE2
|
`ifdef PCI_IMAGE2
|
PCI_DECODER #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder2
|
PCI_DECODER #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder2
|
(.hit (hit2_in),
|
(.hit (hit2_in),
|
.addr_out (address2_in),
|
.addr_out (address2_in),
|
.addr_in (address_in),
|
.addr_in (address_in),
|
|
.bc_in (bc_in),
|
.base_addr (pci_base_addr2_in),
|
.base_addr (pci_base_addr2_in),
|
.mask_addr (pci_addr_mask2_in),
|
.mask_addr (pci_addr_mask2_in),
|
.tran_addr (pci_tran_addr2_in),
|
.tran_addr (pci_tran_addr2_in),
|
.at_en (addr_tran_en2_in),
|
.at_en (addr_tran_en2_in),
|
.mem_io_space (mem_io_addr_space2_in),
|
.mem_io_space (mem_io_addr_space2_in),
|
.mem_en (mem_enable_in),
|
.mem_en (mem_enable_in),
|
.io_en (io_enable_in)
|
.io_en (io_enable_in)
|
) ;
|
) ;
|
`endif
|
`endif
|
`ifdef PCI_IMAGE3
|
`ifdef PCI_IMAGE3
|
PCI_DECODER #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder2
|
|
(.hit (hit2_in),
|
|
.addr_out (address2_in),
|
|
.addr_in (address_in),
|
|
.base_addr (pci_base_addr2_in),
|
|
.mask_addr (pci_addr_mask2_in),
|
|
.tran_addr (pci_tran_addr2_in),
|
|
.at_en (addr_tran_en2_in),
|
|
.mem_io_space (mem_io_addr_space2_in),
|
|
.mem_en (mem_enable_in),
|
|
.io_en (io_enable_in)
|
|
) ;
|
|
PCI_DECODER #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder3
|
PCI_DECODER #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder3
|
(.hit (hit3_in),
|
(.hit (hit3_in),
|
.addr_out (address3_in),
|
.addr_out (address3_in),
|
.addr_in (address_in),
|
.addr_in (address_in),
|
|
.bc_in (bc_in),
|
.base_addr (pci_base_addr3_in),
|
.base_addr (pci_base_addr3_in),
|
.mask_addr (pci_addr_mask3_in),
|
.mask_addr (pci_addr_mask3_in),
|
.tran_addr (pci_tran_addr3_in),
|
.tran_addr (pci_tran_addr3_in),
|
.at_en (addr_tran_en3_in),
|
.at_en (addr_tran_en3_in),
|
.mem_io_space (mem_io_addr_space3_in),
|
.mem_io_space (mem_io_addr_space3_in),
|
.mem_en (mem_enable_in),
|
.mem_en (mem_enable_in),
|
.io_en (io_enable_in)
|
.io_en (io_enable_in)
|
) ;
|
) ;
|
`endif
|
`endif
|
`ifdef PCI_IMAGE4
|
`ifdef PCI_IMAGE4
|
PCI_DECODER #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder2
|
|
(.hit (hit2_in),
|
|
.addr_out (address2_in),
|
|
.addr_in (address_in),
|
|
.base_addr (pci_base_addr2_in),
|
|
.mask_addr (pci_addr_mask2_in),
|
|
.tran_addr (pci_tran_addr2_in),
|
|
.at_en (addr_tran_en2_in),
|
|
.mem_io_space (mem_io_addr_space2_in),
|
|
.mem_en (mem_enable_in),
|
|
.io_en (io_enable_in)
|
|
) ;
|
|
PCI_DECODER #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder3
|
|
(.hit (hit3_in),
|
|
.addr_out (address3_in),
|
|
.addr_in (address_in),
|
|
.base_addr (pci_base_addr3_in),
|
|
.mask_addr (pci_addr_mask3_in),
|
|
.tran_addr (pci_tran_addr3_in),
|
|
.at_en (addr_tran_en3_in),
|
|
.mem_io_space (mem_io_addr_space3_in),
|
|
.mem_en (mem_enable_in),
|
|
.io_en (io_enable_in)
|
|
) ;
|
|
PCI_DECODER #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder4
|
PCI_DECODER #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder4
|
(.hit (hit4_in),
|
(.hit (hit4_in),
|
.addr_out (address4_in),
|
.addr_out (address4_in),
|
.addr_in (address_in),
|
.addr_in (address_in),
|
|
.bc_in (bc_in),
|
.base_addr (pci_base_addr4_in),
|
.base_addr (pci_base_addr4_in),
|
.mask_addr (pci_addr_mask4_in),
|
.mask_addr (pci_addr_mask4_in),
|
.tran_addr (pci_tran_addr4_in),
|
.tran_addr (pci_tran_addr4_in),
|
.at_en (addr_tran_en4_in),
|
.at_en (addr_tran_en4_in),
|
.mem_io_space (mem_io_addr_space4_in),
|
.mem_io_space (mem_io_addr_space4_in),
|
.mem_en (mem_enable_in),
|
.mem_en (mem_enable_in),
|
.io_en (io_enable_in)
|
.io_en (io_enable_in)
|
) ;
|
) ;
|
`endif
|
`endif
|
`ifdef PCI_IMAGE5
|
`ifdef PCI_IMAGE5
|
PCI_DECODER #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder2
|
|
(.hit (hit2_in),
|
|
.addr_out (address2_in),
|
|
.addr_in (address_in),
|
|
.base_addr (pci_base_addr2_in),
|
|
.mask_addr (pci_addr_mask2_in),
|
|
.tran_addr (pci_tran_addr2_in),
|
|
.at_en (addr_tran_en2_in),
|
|
.mem_io_space (mem_io_addr_space2_in),
|
|
.mem_en (mem_enable_in),
|
|
.io_en (io_enable_in)
|
|
) ;
|
|
PCI_DECODER #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder3
|
|
(.hit (hit3_in),
|
|
.addr_out (address3_in),
|
|
.addr_in (address_in),
|
|
.base_addr (pci_base_addr3_in),
|
|
.mask_addr (pci_addr_mask3_in),
|
|
.tran_addr (pci_tran_addr3_in),
|
|
.at_en (addr_tran_en3_in),
|
|
.mem_io_space (mem_io_addr_space3_in),
|
|
.mem_en (mem_enable_in),
|
|
.io_en (io_enable_in)
|
|
) ;
|
|
PCI_DECODER #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder4
|
|
(.hit (hit4_in),
|
|
.addr_out (address4_in),
|
|
.addr_in (address_in),
|
|
.base_addr (pci_base_addr4_in),
|
|
.mask_addr (pci_addr_mask4_in),
|
|
.tran_addr (pci_tran_addr4_in),
|
|
.at_en (addr_tran_en4_in),
|
|
.mem_io_space (mem_io_addr_space4_in),
|
|
.mem_en (mem_enable_in),
|
|
.io_en (io_enable_in)
|
|
) ;
|
|
PCI_DECODER #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder5
|
|
(.hit (hit5_in),
|
|
.addr_out (address5_in),
|
|
.addr_in (address_in),
|
|
.base_addr (pci_base_addr5_in),
|
|
.mask_addr (pci_addr_mask5_in),
|
|
.tran_addr (pci_tran_addr5_in),
|
|
.at_en (addr_tran_en5_in),
|
|
.mem_io_space (mem_io_addr_space5_in),
|
|
.mem_en (mem_enable_in),
|
|
.io_en (io_enable_in)
|
|
) ;
|
|
`endif
|
|
`ifdef PCI_IMAGE6
|
|
PCI_DECODER #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder2
|
|
(.hit (hit2_in),
|
|
.addr_out (address2_in),
|
|
.addr_in (address_in),
|
|
.base_addr (pci_base_addr2_in),
|
|
.mask_addr (pci_addr_mask2_in),
|
|
.tran_addr (pci_tran_addr2_in),
|
|
.at_en (addr_tran_en2_in),
|
|
.mem_io_space (mem_io_addr_space2_in),
|
|
.mem_en (mem_enable_in),
|
|
.io_en (io_enable_in)
|
|
) ;
|
|
PCI_DECODER #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder3
|
|
(.hit (hit3_in),
|
|
.addr_out (address3_in),
|
|
.addr_in (address_in),
|
|
.base_addr (pci_base_addr3_in),
|
|
.mask_addr (pci_addr_mask3_in),
|
|
.tran_addr (pci_tran_addr3_in),
|
|
.at_en (addr_tran_en3_in),
|
|
.mem_io_space (mem_io_addr_space3_in),
|
|
.mem_en (mem_enable_in),
|
|
.io_en (io_enable_in)
|
|
) ;
|
|
PCI_DECODER #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder4
|
|
(.hit (hit4_in),
|
|
.addr_out (address4_in),
|
|
.addr_in (address_in),
|
|
.base_addr (pci_base_addr4_in),
|
|
.mask_addr (pci_addr_mask4_in),
|
|
.tran_addr (pci_tran_addr4_in),
|
|
.at_en (addr_tran_en4_in),
|
|
.mem_io_space (mem_io_addr_space4_in),
|
|
.mem_en (mem_enable_in),
|
|
.io_en (io_enable_in)
|
|
) ;
|
|
PCI_DECODER #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder5
|
PCI_DECODER #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder5
|
(.hit (hit5_in),
|
(.hit (hit5_in),
|
.addr_out (address5_in),
|
.addr_out (address5_in),
|
.addr_in (address_in),
|
.addr_in (address_in),
|
|
.bc_in (bc_in),
|
.base_addr (pci_base_addr5_in),
|
.base_addr (pci_base_addr5_in),
|
.mask_addr (pci_addr_mask5_in),
|
.mask_addr (pci_addr_mask5_in),
|
.tran_addr (pci_tran_addr5_in),
|
.tran_addr (pci_tran_addr5_in),
|
.at_en (addr_tran_en5_in),
|
.at_en (addr_tran_en5_in),
|
.mem_io_space (mem_io_addr_space5_in),
|
.mem_io_space (mem_io_addr_space5_in),
|
| Line 588... |
Line 544... |
reg addr_claim ;// address claim signal is asinchronous set for addr_claim_out signal to PCI Target SM
|
reg addr_claim ;// address claim signal is asinchronous set for addr_claim_out signal to PCI Target SM
|
|
|
// Determining if image 0 is assigned to configuration space or as normal pci to wb access!
|
// Determining if image 0 is assigned to configuration space or as normal pci to wb access!
|
// if normal access is allowed to configuration space, then hit0 is hit0_conf
|
// if normal access is allowed to configuration space, then hit0 is hit0_conf
|
`ifdef HOST
|
`ifdef HOST
|
`ifdef PCI_IMAGE6
|
`ifdef NO_CNF_IMAGE
|
parameter hit0_conf = 1'b0 ;
|
parameter hit0_conf = 1'b0 ;
|
`else
|
`else
|
parameter hit0_conf = 1'b1 ; // if normal access is allowed to configuration space, then hit0 is hit0_conf
|
parameter hit0_conf = 1'b1 ; // if normal access is allowed to configuration space, then hit0 is hit0_conf
|
`endif
|
`endif
|
`else
|
`else // GUEST
|
parameter hit0_conf = 1'b1 ; // if normal access is allowed to configuration space, then hit0 is hit0_conf
|
parameter hit0_conf = 1'b1 ; // if normal access is allowed to configuration space, then hit0 is hit0_conf
|
`endif
|
`endif
|
|
|
// Logic with address mux, determining if address is still in the same image space and if it is prefetced or not
|
// Logic with address mux, determining if address is still in the same image space and if it is prefetced or not
|
`ifdef PCI_IMAGE6
|
|
always@(hit5_in or hit4_in or hit3_in or hit2_in or hit1_in or hit0_in or
|
|
address5_in or address4_in or address3_in or address2_in or address1_in or address0_in or
|
|
pre_fetch_en5_in or
|
|
pre_fetch_en4_in or
|
|
pre_fetch_en3_in or
|
|
pre_fetch_en2_in or
|
|
pre_fetch_en1_in or
|
|
pre_fetch_en0_in
|
|
)
|
|
begin
|
|
addr_claim <= (hit5_in || hit4_in || hit3_in || hit2_in) || (hit1_in || hit0_in) ;
|
|
case ({hit5_in, hit4_in, hit3_in, hit2_in, hit1_in, hit0_in})
|
|
6'b010000 :
|
|
begin
|
|
address <= address4_in ;
|
|
pre_fetch_en <= pre_fetch_en4_in ;
|
|
end
|
|
6'b001000 :
|
|
begin
|
|
address <= address3_in ;
|
|
pre_fetch_en <= pre_fetch_en3_in ;
|
|
end
|
|
6'b000100 :
|
|
begin
|
|
address <= address2_in ;
|
|
pre_fetch_en <= pre_fetch_en2_in ;
|
|
end
|
|
6'b000010 :
|
|
begin
|
|
address <= address1_in ;
|
|
pre_fetch_en <= pre_fetch_en1_in ;
|
|
end
|
|
6'b000001 :
|
|
begin
|
|
address <= address0_in ;
|
|
pre_fetch_en <= pre_fetch_en0_in ;
|
|
end
|
|
default :
|
|
begin
|
|
address <= address5_in ;
|
|
pre_fetch_en <= pre_fetch_en5_in ;
|
|
end
|
|
endcase
|
|
end
|
|
`else
|
|
`ifdef PCI_IMAGE5
|
|
always@(hit5_in or hit4_in or hit3_in or hit2_in or hit1_in or hit0_in or
|
always@(hit5_in or hit4_in or hit3_in or hit2_in or hit1_in or hit0_in or
|
address5_in or address4_in or address3_in or address2_in or address1_in or address0_in or
|
address5_in or address4_in or address3_in or address2_in or address1_in or address0_in or
|
pre_fetch_en5_in or
|
pre_fetch_en5 or
|
pre_fetch_en4_in or
|
pre_fetch_en4 or
|
pre_fetch_en3_in or
|
pre_fetch_en3 or
|
pre_fetch_en2_in or
|
pre_fetch_en2 or
|
pre_fetch_en1_in or
|
pre_fetch_en1 or
|
pre_fetch_en0_in
|
pre_fetch_en0
|
)
|
)
|
begin
|
begin
|
addr_claim <= (hit5_in || hit4_in || hit3_in || hit2_in) || (hit1_in || hit0_in) ;
|
addr_claim <= (hit5_in || hit4_in) || (hit3_in || hit2_in || hit1_in || hit0_in) ;
|
case ({hit5_in, hit4_in, hit3_in, hit2_in, hit1_in, hit0_in})
|
case ({hit5_in, hit4_in, hit3_in, hit2_in, hit0_in})
|
6'b010000 :
|
5'b10000 :
|
begin
|
|
address <= address4_in ;
|
|
pre_fetch_en <= pre_fetch_en4_in ;
|
|
end
|
|
6'b001000 :
|
|
begin
|
|
address <= address3_in ;
|
|
pre_fetch_en <= pre_fetch_en3_in ;
|
|
end
|
|
6'b000100 :
|
|
begin
|
|
address <= address2_in ;
|
|
pre_fetch_en <= pre_fetch_en2_in ;
|
|
end
|
|
6'b000010 :
|
|
begin
|
|
address <= address1_in ;
|
|
pre_fetch_en <= pre_fetch_en1_in ;
|
|
end
|
|
6'b000001 :
|
|
begin
|
|
address <= address0_in ;
|
|
pre_fetch_en <= pre_fetch_en0_in ;
|
|
end
|
|
default :
|
|
begin
|
begin
|
address <= address5_in ;
|
address <= address5_in ;
|
pre_fetch_en <= pre_fetch_en5_in ;
|
pre_fetch_en <= pre_fetch_en5 ;
|
end
|
end
|
endcase
|
|
end
|
|
`else
|
|
`ifdef PCI_IMAGE4
|
|
always@(hit4_in or hit3_in or hit2_in or hit1_in or hit0_in or
|
|
address4_in or address3_in or address2_in or address1_in or address0_in or
|
|
pre_fetch_en4_in or
|
|
pre_fetch_en3_in or
|
|
pre_fetch_en2_in or
|
|
pre_fetch_en1_in or
|
|
pre_fetch_en0_in
|
|
)
|
|
begin
|
|
addr_claim <= hit4_in || (hit3_in || hit2_in || hit1_in || hit0_in) ;
|
|
case ({hit4_in, hit3_in, hit2_in, hit1_in, hit0_in})
|
|
5'b01000 :
|
5'b01000 :
|
begin
|
begin
|
address <= address3_in ;
|
address <= address4_in ;
|
pre_fetch_en <= pre_fetch_en3_in ;
|
pre_fetch_en <= pre_fetch_en4 ;
|
end
|
end
|
5'b00100 :
|
5'b00100 :
|
begin
|
begin
|
address <= address2_in ;
|
address <= address3_in ;
|
pre_fetch_en <= pre_fetch_en2_in ;
|
pre_fetch_en <= pre_fetch_en3 ;
|
end
|
end
|
5'b00010 :
|
5'b00010 :
|
begin
|
begin
|
address <= address1_in ;
|
address <= address2_in ;
|
pre_fetch_en <= pre_fetch_en1_in ;
|
pre_fetch_en <= pre_fetch_en2 ;
|
end
|
end
|
5'b00001 :
|
5'b00001 :
|
begin
|
begin
|
address <= address0_in ;
|
address <= address0_in ;
|
pre_fetch_en <= pre_fetch_en0_in ;
|
pre_fetch_en <= pre_fetch_en0 ;
|
end
|
end
|
default :
|
default : // IMAGE 1 is always included into PCI bridge
|
begin
|
|
address <= address4_in ;
|
|
pre_fetch_en <= pre_fetch_en4_in ;
|
|
end
|
|
endcase
|
|
end
|
|
`else
|
|
`ifdef PCI_IMAGE3
|
|
always@(hit3_in or hit2_in or hit1_in or hit0_in or
|
|
address3_in or address2_in or address1_in or address0_in or
|
|
pre_fetch_en3_in or
|
|
pre_fetch_en2_in or
|
|
pre_fetch_en1_in or
|
|
pre_fetch_en0_in
|
|
)
|
|
begin
|
|
addr_claim <= (hit3_in || hit2_in || hit1_in || hit0_in) ;
|
|
case ({hit3_in, hit2_in, hit1_in, hit0_in})
|
|
4'b0100 :
|
|
begin
|
|
address <= address2_in ;
|
|
pre_fetch_en <= pre_fetch_en2_in ;
|
|
end
|
|
4'b0010 :
|
|
begin
|
begin
|
address <= address1_in ;
|
address <= address1_in ;
|
pre_fetch_en <= pre_fetch_en1_in ;
|
pre_fetch_en <= pre_fetch_en1 ;
|
end
|
|
4'b0001 :
|
|
begin
|
|
address <= address0_in ;
|
|
pre_fetch_en <= pre_fetch_en0_in ;
|
|
end
|
|
default :
|
|
begin
|
|
address <= address3_in ;
|
|
pre_fetch_en <= pre_fetch_en3_in ;
|
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
`else
|
|
`ifdef PCI_IMAGE2
|
// Address claim output to PCI Target SM
|
always@(hit2_in or hit1_in or hit0_in or
|
assign addr_claim_out = addr_claim ;
|
address2_in or address1_in or address0_in or
|
|
pre_fetch_en2_in or
|
reg [31:0] norm_address ; // stored normal address (decoded and translated) for access to WB
|
pre_fetch_en1_in or
|
reg norm_prf_en ; // stored pre-fetch enable
|
pre_fetch_en0_in
|
reg [3:0] norm_bc ; // stored bus-command
|
)
|
reg same_read_reg ; // stored SAME_READ information
|
begin
|
reg target_rd ; // delayed registered TRDY output equivalent signal
|
addr_claim <= (hit2_in || hit1_in || hit0_in) ;
|
|
case ({hit2_in, hit1_in, hit0_in})
|
always@(posedge clk_in or posedge reset_in)
|
3'b010 :
|
|
begin
|
|
address <= address1_in ;
|
|
pre_fetch_en <= pre_fetch_en1_in ;
|
|
end
|
|
3'b001 :
|
|
begin
|
begin
|
address <= address0_in ;
|
if (reset_in)
|
pre_fetch_en <= pre_fetch_en0_in ;
|
|
end
|
|
default :
|
|
begin
|
begin
|
address <= address2_in ;
|
norm_address <= #`FF_DELAY 32'h0000_0000 ;
|
pre_fetch_en <= pre_fetch_en2_in ;
|
norm_prf_en <= #`FF_DELAY 1'b0 ;
|
|
norm_bc <= #`FF_DELAY 4'h0 ;
|
|
same_read_reg <= #`FF_DELAY 1'b0 ;
|
end
|
end
|
endcase
|
else
|
end
|
|
`else
|
|
always@(hit1_in or hit0_in or
|
|
address1_in or address0_in or
|
|
pre_fetch_en1_in or
|
|
pre_fetch_en0_in
|
|
)
|
|
begin
|
begin
|
addr_claim <= (hit1_in || hit0_in) ;
|
if (addr_phase_in)
|
case ({hit1_in, hit0_in})
|
|
2'b01 :
|
|
begin
|
begin
|
address <= address0_in ;
|
norm_address <= #`FF_DELAY address ;
|
pre_fetch_en <= pre_fetch_en0_in ;
|
norm_prf_en <= #`FF_DELAY pre_fetch_en ;
|
|
norm_bc <= #`FF_DELAY bc_in ;
|
|
same_read_reg <= #`FF_DELAY same_read_out ;
|
end
|
end
|
default :
|
|
begin
|
|
address <= address1_in ;
|
|
pre_fetch_en <= pre_fetch_en1_in ;
|
|
end
|
end
|
endcase
|
|
end
|
end
|
`endif
|
|
`endif
|
|
`endif
|
|
`endif
|
|
`endif
|
|
|
|
// Address claim output to PCI Target SM
|
|
assign addr_claim_out = addr_claim ;
|
|
|
|
|
`ifdef HOST
|
|
`ifdef NO_CNF_IMAGE
|
|
reg [1:0] strd_address ; // stored INPUT address for accessing Configuration space registers
|
|
`else
|
reg [11:0] strd_address ; // stored INPUT address for accessing Configuration space registers
|
reg [11:0] strd_address ; // stored INPUT address for accessing Configuration space registers
|
reg [31:0] norm_address ; // stored normal address (decoded and translated) for access to WB
|
`endif
|
reg norm_prf_en ; // stored pre-fetch enable
|
`else
|
reg [3:0] norm_bc ; // stored bus-command
|
reg [11:0] strd_address ; // stored INPUT address for accessing Configuration space registers
|
reg same_read_reg ; // stored SAME_READ information
|
`endif
|
reg bckp_trdy_reg ; // delayed registered TRDY output equivalent signal
|
|
reg trdy_asserted_reg ; // delayed bckp_trdy_reg signal
|
|
|
|
always@(posedge clk_in or posedge reset_in)
|
always@(posedge clk_in or posedge reset_in)
|
begin
|
begin
|
if (reset_in)
|
if (reset_in)
|
begin
|
begin
|
strd_address <= 12'h000 ;
|
strd_address <= #`FF_DELAY 0 ;
|
norm_address <= 32'h0000_0000 ;
|
|
norm_prf_en <= 1'b0 ;
|
|
norm_bc <= 4'h0 ;
|
|
same_read_reg <= 1'b0 ;
|
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if (addr_phase_in)
|
if (addr_phase_in)
|
begin
|
begin
|
strd_address <= address_in[11:0] ;
|
`ifdef HOST
|
norm_address <= address ;
|
`ifdef NO_CNF_IMAGE
|
norm_prf_en <= pre_fetch_en ;
|
strd_address <= #`FF_DELAY address_in[1:0] ;
|
norm_bc <= bc_in ;
|
`else
|
same_read_reg <= same_read_out ;
|
strd_address <= #`FF_DELAY address_in[11:0] ;
|
|
`endif
|
|
`else
|
|
strd_address <= #`FF_DELAY address_in[11:0] ;
|
|
`endif
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
always@(posedge clk_in or posedge reset_in)
|
always@(posedge clk_in or posedge reset_in)
|
begin
|
begin
|
if (reset_in)
|
if (reset_in)
|
begin
|
begin
|
bckp_trdy_reg <= 1'b0 ;
|
target_rd <= #`FF_DELAY 1'b0 ;
|
trdy_asserted_reg <= 1'b0 ;
|
|
end
|
end
|
else
|
else
|
begin
|
begin
|
bckp_trdy_reg <= bckp_trdy_in ;
|
if (same_read_reg && !bckp_trdy_in)
|
trdy_asserted_reg <= bckp_trdy_reg ;
|
target_rd <= #`FF_DELAY 1'b1 ;// Signal indicates when target ready is deaserted on PCI bus
|
|
else if (same_read_reg && bckp_devsel_in && !bckp_stop_in)
|
|
target_rd <= #`FF_DELAY 1'b1 ;// Signal indicates when target ready is deaserted on PCI bus
|
|
else if (!same_read_reg)
|
|
target_rd <= #`FF_DELAY 1'b0 ;// Signal indicates when target ready is deaserted on PCI bus
|
end
|
end
|
end
|
end
|
// Signal indicates when target ready is deaserted on PCI bus
|
// '1' indicates asserted TRDY signal when same read operation is performed
|
wire trdy_asserted = trdy_asserted_reg && bckp_trdy_reg ;
|
wire target_rd_completed = target_rd ;
|
|
|
reg same_read_request ;
|
reg same_read_request ;
|
|
|
// When delayed read is completed on WB, addres and bc must be compered, if there is the same read request
|
// When delayed read is completed on WB, addres and bc must be compered, if there is the same read request
|
always@(address or strd_addr_in or bc_in or strd_bc_in)
|
always@(address or strd_addr_in or bc_in or strd_bc_in)
|
| Line 918... |
Line 731... |
endcase
|
endcase
|
end
|
end
|
|
|
reg calc_target_abort ;
|
reg calc_target_abort ;
|
// Target abort indication regarding the registered bus command and current signals for byte enable checking
|
// Target abort indication regarding the registered bus command and current signals for byte enable checking
|
always@(bc_in or hit0_in or io_be_ok or conf_be_ok)
|
always@(norm_bc or hit0_in or io_be_ok or conf_be_ok)
|
begin
|
begin
|
case (bc_in)
|
case (norm_bc)
|
// READ COMMANDS
|
// READ COMMANDS
|
`BC_IO_READ :
|
`BC_IO_READ :
|
begin
|
begin
|
case ({hit0_in, hit0_conf})
|
case ({hit0_in, hit0_conf})
|
|
`ifdef HOST
|
|
`ifdef NO_CNF_IMAGE
|
|
`else
|
|
2'b11 :
|
|
begin
|
|
calc_target_abort <= 1'b1 ;
|
|
end
|
|
`endif
|
|
`else
|
2'b11 :
|
2'b11 :
|
begin
|
begin
|
calc_target_abort <= 1'b1 ;
|
calc_target_abort <= 1'b1 ;
|
end
|
end
|
|
`endif
|
default :
|
default :
|
begin
|
begin
|
if (io_be_ok)
|
if (io_be_ok)
|
begin
|
begin
|
calc_target_abort <= 1'b0 ;
|
calc_target_abort <= 1'b0 ;
|
| Line 944... |
Line 767... |
end
|
end
|
endcase
|
endcase
|
end
|
end
|
`BC_MEM_READ :
|
`BC_MEM_READ :
|
begin
|
begin
|
case ({hit0_in, hit0_conf})
|
|
2'b11 :
|
|
begin
|
|
calc_target_abort <= 1'b0 ;
|
calc_target_abort <= 1'b0 ;
|
end
|
end
|
default :
|
|
begin
|
|
calc_target_abort <= 1'b0 ;
|
|
end
|
|
endcase
|
|
end
|
|
`BC_CONF_READ :
|
`BC_CONF_READ :
|
begin
|
begin
|
case (conf_be_ok)
|
case (conf_be_ok)
|
1'b1 :
|
1'b1 :
|
begin
|
begin
|
| Line 972... |
Line 786... |
end
|
end
|
`BC_MEM_READ_LN,
|
`BC_MEM_READ_LN,
|
`BC_MEM_READ_MUL :
|
`BC_MEM_READ_MUL :
|
begin
|
begin
|
case ({hit0_in, hit0_conf})
|
case ({hit0_in, hit0_conf})
|
|
`ifdef HOST
|
|
`ifdef NO_CNF_IMAGE
|
|
`else
|
|
2'b11 :
|
|
begin
|
|
calc_target_abort <= 1'b1 ;
|
|
end
|
|
`endif
|
|
`else
|
2'b11 :
|
2'b11 :
|
begin
|
begin
|
calc_target_abort <= 1'b1 ;
|
calc_target_abort <= 1'b1 ;
|
end
|
end
|
|
`endif
|
default :
|
default :
|
begin
|
begin
|
calc_target_abort <= 1'b0 ;
|
calc_target_abort <= 1'b0 ;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
// WRITE COMMANDS
|
// WRITE COMMANDS
|
`BC_IO_WRITE :
|
`BC_IO_WRITE :
|
begin
|
begin
|
case ({hit0_in, hit0_conf})
|
case ({hit0_in, hit0_conf})
|
|
`ifdef HOST
|
|
`ifdef NO_CNF_IMAGE
|
|
`else
|
|
2'b11 :
|
|
begin
|
|
calc_target_abort <= 1'b1 ;
|
|
end
|
|
`endif
|
|
`else
|
2'b11 :
|
2'b11 :
|
begin
|
begin
|
calc_target_abort <= 1'b1 ;
|
calc_target_abort <= 1'b1 ;
|
end
|
end
|
|
`endif
|
default :
|
default :
|
begin
|
begin
|
if (io_be_ok)
|
if (io_be_ok)
|
begin
|
begin
|
calc_target_abort <= 1'b0 ;
|
calc_target_abort <= 1'b0 ;
|
| Line 1005... |
Line 839... |
end
|
end
|
endcase
|
endcase
|
end
|
end
|
`BC_MEM_WRITE :
|
`BC_MEM_WRITE :
|
begin
|
begin
|
case ({hit0_in, hit0_conf})
|
|
2'b11 :
|
|
begin
|
|
calc_target_abort <= 1'b0 ;
|
calc_target_abort <= 1'b0 ;
|
end
|
end
|
default :
|
|
begin
|
|
calc_target_abort <= 1'b0 ;
|
|
end
|
|
endcase
|
|
end
|
|
`BC_CONF_WRITE :
|
`BC_CONF_WRITE :
|
begin
|
begin
|
case (conf_be_ok)
|
case (conf_be_ok)
|
1'b1 :
|
1'b1 :
|
begin
|
begin
|
| Line 1032... |
Line 857... |
endcase
|
endcase
|
end
|
end
|
`BC_MEM_WRITE_INVAL :
|
`BC_MEM_WRITE_INVAL :
|
begin
|
begin
|
case ({hit0_in, hit0_conf})
|
case ({hit0_in, hit0_conf})
|
|
`ifdef HOST
|
|
`ifdef NO_CNF_IMAGE
|
|
`else
|
|
2'b11 :
|
|
begin
|
|
calc_target_abort <= 1'b1 ;
|
|
end
|
|
`endif
|
|
`else
|
2'b11 :
|
2'b11 :
|
begin
|
begin
|
calc_target_abort <= 1'b1 ;
|
calc_target_abort <= 1'b1 ;
|
end
|
end
|
|
`endif
|
default :
|
default :
|
begin
|
begin
|
calc_target_abort <= 1'b0 ;
|
calc_target_abort <= 1'b0 ;
|
end
|
end
|
endcase
|
endcase
|
| Line 1049... |
Line 884... |
calc_target_abort <= 1'b0 ;
|
calc_target_abort <= 1'b0 ;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
|
wire [3:0] pcir_fifo_control_input = pcir_fifo_empty_in ? 4'h0 : pcir_fifo_control_in ;
|
|
|
// Medium registers for data and control busses from PCIR_FIFO
|
// Medium registers for data and control busses from PCIR_FIFO
|
reg [31:0] pcir_fifo_data_reg ;
|
reg [31:0] pcir_fifo_data_reg ;
|
reg [3:0] pcir_fifo_ctrl_reg ;
|
reg [3:0] pcir_fifo_ctrl_reg ;
|
|
|
always@(posedge clk_in or posedge reset_in)
|
always@(posedge clk_in or posedge reset_in)
|
begin
|
begin
|
if (reset_in)
|
if (reset_in)
|
begin
|
begin
|
pcir_fifo_data_reg <= 32'h0000_0000 ;
|
pcir_fifo_data_reg <= #`FF_DELAY 32'h0000_0000 ;
|
pcir_fifo_ctrl_reg <= 4'h0 ;
|
pcir_fifo_ctrl_reg <= #`FF_DELAY 4'h0 ;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if (load_medium_reg_in)
|
if (load_medium_reg_in)
|
begin
|
begin
|
pcir_fifo_data_reg <= pcir_fifo_data_in ;
|
pcir_fifo_data_reg <= #`FF_DELAY pcir_fifo_data_in ;
|
pcir_fifo_ctrl_reg <= pcir_fifo_control_in ;
|
pcir_fifo_ctrl_reg <= #`FF_DELAY pcir_fifo_control_input ;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
// selecting "fifo data" from medium registers or from PCIR_FIFO
|
// selecting "fifo data" from medium registers or from PCIR_FIFO
|
wire [31:0] pcir_fifo_data = sel_fifo_mreg_in ? pcir_fifo_data_in : pcir_fifo_data_reg ;
|
wire [31:0] pcir_fifo_data = (sel_fifo_mreg_in && !pcir_fifo_empty_in) ? pcir_fifo_data_in : pcir_fifo_data_reg ;
|
wire [3:0] pcir_fifo_ctrl = sel_fifo_mreg_in ? pcir_fifo_control_in : pcir_fifo_ctrl_reg ;
|
wire [3:0] pcir_fifo_ctrl = (sel_fifo_mreg_in && !pcir_fifo_empty_in) ? pcir_fifo_control_input : pcir_fifo_ctrl_reg ;
|
|
|
// signal assignments to PCI Target FSM
|
// signal assignments to PCI Target FSM
|
assign norm_access_to_config_out = (hit0_in && hit0_conf) ;
|
|
assign read_completed_out = req_comp_pending_in ; // completion pending input for requesting side of the bridge
|
assign read_completed_out = req_comp_pending_in ; // completion pending input for requesting side of the bridge
|
assign read_processing_out = req_req_pending_in ; // request pending input for requesting side
|
assign read_processing_out = req_req_pending_in ; // request pending input for requesting side
|
|
// when '1', the bus command is IO command - not supported commands are checked in pci_decoder modules
|
|
wire io_memory_bus_command = !norm_bc[3] && !norm_bc[2] ;
|
assign disconect_wo_data_out = (
|
assign disconect_wo_data_out = (
|
((pcir_fifo_ctrl[`LAST_CTRL_BIT] || pcir_fifo_empty_in || ~addr_burst_ok) && ~bc0_in && ~frame_reg_in) ||
|
((/*pcir_fifo_ctrl[`LAST_CTRL_BIT] ||*/ pcir_fifo_empty_in || ~burst_ok_out/*addr_burst_ok*/ || io_memory_bus_command) &&
|
((pciw_fifo_full_in || pciw_fifo_almost_full_in || pciw_fifo_two_left_in || ~addr_burst_ok) && bc0_in && ~frame_reg_in)
|
~bc0_in && ~frame_reg_in) ||
|
|
((pciw_fifo_full_in || pciw_fifo_almost_full_in || pciw_fifo_two_left_in || ~addr_burst_ok || io_memory_bus_command) &&
|
|
bc0_in && ~frame_reg_in)
|
|
) ;
|
|
assign disconect_w_data_out = (
|
|
( burst_ok_out && !io_memory_bus_command && ~bc0_in ) ||
|
|
( addr_burst_ok && !io_memory_bus_command && bc0_in )
|
) ;
|
) ;
|
assign target_abort_out = (addr_phase_in && calc_target_abort) ;
|
assign target_abort_out = ( ~addr_phase_in && calc_target_abort ) ;
|
|
|
|
`ifdef HOST
|
|
`ifdef NO_CNF_IMAGE
|
|
// signal assignments to PCI Target FSM
|
|
assign norm_access_to_config_out = 1'b0 ;
|
// control signal assignments to read request sinchronization module
|
// control signal assignments to read request sinchronization module
|
assign done_out = (~sel_conf_fifo_in && same_read_reg && ~trdy_asserted && last_reg_in) ;
|
assign done_out = (target_rd_completed && last_reg_in) ;
|
|
assign in_progress_out = (same_read_reg && ~bckp_trdy_in) ;
|
|
// signal used for PCIR_FIFO flush (with comp_flush_in signal)
|
|
wire pcir_fifo_flush = (target_rd_completed && last_reg_in && ~pcir_fifo_empty_in) ;
|
|
`else
|
|
// signal assignments to PCI Target FSM
|
|
assign norm_access_to_config_out = (hit0_in && hit0_conf) ;
|
|
// control signal assignments to read request sinchronization module
|
|
assign done_out = (~sel_conf_fifo_in && target_rd_completed && last_reg_in) ;
|
assign in_progress_out = (~sel_conf_fifo_in && same_read_reg && ~bckp_trdy_in) ;
|
assign in_progress_out = (~sel_conf_fifo_in && same_read_reg && ~bckp_trdy_in) ;
|
|
|
// signal used for PCIR_FIFO flush (with comp_flush_in signal)
|
// signal used for PCIR_FIFO flush (with comp_flush_in signal)
|
wire pcir_fifo_flush = (~sel_conf_fifo_in && same_read_reg && ~trdy_asserted && last_reg_in && ~pcir_fifo_empty_in) ;
|
wire pcir_fifo_flush = (~sel_conf_fifo_in && target_rd_completed && last_reg_in && ~pcir_fifo_empty_in) ;
|
|
`endif
|
|
`else
|
|
// signal assignments to PCI Target FSM
|
|
assign norm_access_to_config_out = (hit0_in && hit0_conf) ;
|
|
// control signal assignments to read request sinchronization module
|
|
assign done_out = (~sel_conf_fifo_in && target_rd_completed && last_reg_in) ;
|
|
assign in_progress_out = (~sel_conf_fifo_in && same_read_reg && ~bckp_trdy_in) ;
|
|
// signal used for PCIR_FIFO flush (with comp_flush_in signal)
|
|
wire pcir_fifo_flush = (~sel_conf_fifo_in && target_rd_completed && last_reg_in && ~pcir_fifo_empty_in) ;
|
|
`endif
|
|
|
// flush signal for PCIR_FIFO must be registered, since it asinchronously resets some status registers
|
// flush signal for PCIR_FIFO must be registered, since it asinchronously resets some status registers
|
reg pcir_fifo_flush_reg ;
|
wire pcir_fifo_flush_reg ;
|
always@(posedge clk_in or posedge reset_in)
|
async_reset_flop async_reset_as_pcir_flush
|
begin
|
(
|
if (reset_in)
|
.data_in (comp_flush_in || pcir_fifo_flush),
|
begin
|
.clk_in (clk_in),
|
pcir_fifo_flush_reg <= 1'b0 ;
|
.async_reset_data_out (pcir_fifo_flush_reg),
|
end
|
.reset_in (reset_in)
|
else
|
) ;
|
begin
|
|
pcir_fifo_flush_reg <= comp_flush_in || pcir_fifo_flush ;
|
|
end
|
|
end
|
|
|
|
// signal assignments from fifo to PCI Target FSM
|
// signal assignments from fifo to PCI Target FSM
|
assign wbw_fifo_empty_out = wbw_fifo_empty_in ;
|
assign wbw_fifo_empty_out = wbw_fifo_empty_in ;
|
|
assign wbu_del_read_comp_pending_out = wbu_del_read_comp_pending_in ;
|
assign pciw_fifo_full_out = (pciw_fifo_full_in || pciw_fifo_almost_full_in || pciw_fifo_two_left_in) ;
|
assign pciw_fifo_full_out = (pciw_fifo_full_in || pciw_fifo_almost_full_in || pciw_fifo_two_left_in) ;
|
assign pcir_fifo_data_err_out = pcir_fifo_ctrl[`DATA_ERROR_CTRL_BIT] ;
|
assign pcir_fifo_data_err_out = pcir_fifo_ctrl[`DATA_ERROR_CTRL_BIT] && !sel_conf_fifo_in ;
|
// signal assignments to fifo
|
// signal assignments to fifo
|
assign pcir_fifo_flush_out = pcir_fifo_flush_reg ;
|
assign pcir_fifo_flush_out = pcir_fifo_flush_reg ;
|
assign pcir_fifo_renable_out = fetch_pcir_fifo_in ;
|
assign pcir_fifo_renable_out = fetch_pcir_fifo_in && !pcir_fifo_empty_in ;
|
assign pciw_fifo_wenable_out = load_to_pciw_fifo_in ;
|
assign pciw_fifo_wenable_out = load_to_pciw_fifo_in ;
|
assign pciw_fifo_control_out[`ADDR_CTRL_BIT] = 1'b0 ;
|
assign pciw_fifo_control_out[`ADDR_CTRL_BIT] = ~rdy_in ;
|
assign pciw_fifo_control_out[`BURST_BIT] = rdy_in ? 1'b0 : ~frame_reg_in ;
|
assign pciw_fifo_control_out[`BURST_BIT] = rdy_in ? ~frame_reg_in : 1'b0 ;
|
assign pciw_fifo_control_out[`DATA_ERROR_CTRL_BIT] = 1'b0 ;
|
assign pciw_fifo_control_out[`DATA_ERROR_CTRL_BIT] = 1'b0 ;
|
assign pciw_fifo_control_out[`LAST_CTRL_BIT] = rdy_in ? (last_reg_in || pciw_fifo_almost_full_in) : 1'b0 ;
|
assign pciw_fifo_control_out[`LAST_CTRL_BIT] = rdy_in ?
|
|
(last_reg_in || pciw_fifo_almost_full_in || ~addr_burst_ok || io_memory_bus_command) : 1'b0 ;
|
|
|
|
`ifdef HOST
|
|
`ifdef NO_CNF_IMAGE
|
|
// data and address outputs assignments to PCI Target FSM
|
|
assign data_out = pcir_fifo_data ;
|
|
`else
|
|
// data and address outputs assignments to PCI Target FSM
|
|
assign data_out = sel_conf_fifo_in ? conf_data_in : pcir_fifo_data ;
|
|
`endif
|
|
`else
|
// data and address outputs assignments to PCI Target FSM
|
// data and address outputs assignments to PCI Target FSM
|
assign data_out = sel_conf_fifo_in ? conf_data_in : pcir_fifo_data ;
|
assign data_out = sel_conf_fifo_in ? conf_data_in : pcir_fifo_data ;
|
|
`endif
|
|
|
// data and address outputs assignments to read request sinchronization module
|
// data and address outputs assignments to read request sinchronization module
|
assign req_out = req_in ;
|
assign req_out = req_in ;
|
assign addr_out = norm_address ;
|
// this address is stored in delayed_sync module and is connected back as strd_addr_in
|
|
assign addr_out = norm_address[31:0] ; // correction of 2 LSBits is done in wb_master module, original address must be saved
|
assign be_out = be_in ;
|
assign be_out = be_in ;
|
assign we_out = 1'b0 ;
|
assign we_out = 1'b0 ;
|
assign bc_out = norm_bc ;
|
assign bc_out = norm_bc ;
|
assign burst_out = ~frame_reg_in && norm_prf_en ;
|
// burst is OK for reads when there is ((MEM_READ_LN or MEM_READ_MUL) and AD[1:0]==2'b00) OR
|
// data and address outputs assignments to PCIW_FIFO
|
// (MEM_READ and Prefetchable_IMAGE and AD[1:0]==2'b00)
|
assign pciw_fifo_addr_data_out = rdy_in ? data_in : norm_address ;
|
assign burst_ok_out = (norm_bc[3] && addr_burst_ok) || (norm_bc[2] && norm_prf_en && addr_burst_ok) ;
|
|
// data and address outputs assignments to PCIW_FIFO - correction of 2 LSBits
|
|
assign pciw_fifo_addr_data_out = rdy_in ? data_in : {norm_address[31:2], norm_address[1] && io_memory_bus_command,
|
|
norm_address[0] && io_memory_bus_command} ;
|
assign pciw_fifo_cbe_out = rdy_in ? be_in : norm_bc ;
|
assign pciw_fifo_cbe_out = rdy_in ? be_in : norm_bc ;
|
// data and address outputs assignments to Configuration space
|
// data and address outputs assignments to Configuration space
|
|
`ifdef HOST
|
|
`ifdef NO_CNF_IMAGE
|
|
assign conf_data_out = 32'h0 ;
|
|
assign conf_addr_out = 12'h0 ;
|
|
assign conf_be_out = 4'b0 ;
|
|
assign conf_we_out = 1'h0 ;
|
|
`else
|
assign conf_data_out = data_in ;
|
assign conf_data_out = data_in ;
|
assign conf_addr_out = strd_address[11:0] ;
|
assign conf_addr_out = strd_address[11:0] ;
|
assign conf_be_out = be_in ;
|
assign conf_be_out = be_in ;
|
assign conf_we_out = load_to_conf_in ;
|
assign conf_we_out = load_to_conf_in ;
|
assign conf_re_out = fetch_conf_in ;
|
`endif
|
|
`else
|
|
assign conf_data_out = data_in ;
|
|
assign conf_addr_out = strd_address[11:0] ;
|
|
assign conf_be_out = be_in ;
|
|
assign conf_we_out = load_to_conf_in ;
|
|
`endif
|
|
// NOT USED NOW, SONCE READ IS ASYNCHRONOUS
|
|
//assign conf_re_out = fetch_conf_in ;
|
|
assign conf_re_out = 1'b0 ;
|
|
|
endmodule
|
endmodule
|
No newline at end of file
|
No newline at end of file
|
|
|
No newline at end of file
|
No newline at end of file
|
