| Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/02/01 15:25:12 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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//
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// Revision 1.2 2001/10/05 08:14:30 mihad
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// Revision 1.2 2001/10/05 08:14:30 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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//
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// New project directory structure
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// New project directory structure
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| Line 673... |
Line 676... |
begin
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begin
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if (same_read_reg && !bckp_trdy_in)
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if (same_read_reg && !bckp_trdy_in)
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target_rd <= #`FF_DELAY 1'b1 ;// Signal indicates when target ready is deaserted on PCI bus
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target_rd <= #`FF_DELAY 1'b1 ;// Signal indicates when target ready is deaserted on PCI bus
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else if (same_read_reg && bckp_devsel_in && !bckp_stop_in)
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else if (same_read_reg && bckp_devsel_in && !bckp_stop_in)
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target_rd <= #`FF_DELAY 1'b1 ;// Signal indicates when target ready is deaserted on PCI bus
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target_rd <= #`FF_DELAY 1'b1 ;// Signal indicates when target ready is deaserted on PCI bus
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else if (!same_read_reg)
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else if ((!same_read_reg) || (last_reg_in && target_rd))
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target_rd <= #`FF_DELAY 1'b0 ;// Signal indicates when target ready is deaserted on PCI bus
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target_rd <= #`FF_DELAY 1'b0 ;// Signal indicates when target ready is deaserted on PCI bus
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end
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end
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end
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end
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// '1' indicates asserted TRDY signal when same read operation is performed
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// '1' indicates asserted TRDY signal when same read operation is performed
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wire target_rd_completed = target_rd ;
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wire target_rd_completed = target_rd ;
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| Line 743... |
Line 746... |
`ifdef HOST
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`ifdef HOST
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`ifdef NO_CNF_IMAGE
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`ifdef NO_CNF_IMAGE
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`else
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`else
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2'b11 :
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2'b11 :
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begin
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begin
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calc_target_abort <= 1'b1 ;
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calc_target_abort <= 1'b0 ;
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end
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end
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`endif
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`endif
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`else
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`else
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2'b11 :
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2'b11 :
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begin
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begin
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calc_target_abort <= 1'b1 ;
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calc_target_abort <= 1'b0 ;
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end
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end
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`endif
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`endif
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default :
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default :
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begin
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begin
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if (io_be_ok)
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if (io_be_ok)
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| Line 785... |
Line 788... |
endcase
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endcase
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end
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end
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`BC_MEM_READ_LN,
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`BC_MEM_READ_LN,
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`BC_MEM_READ_MUL :
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`BC_MEM_READ_MUL :
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begin
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begin
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case ({hit0_in, hit0_conf})
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`ifdef HOST
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`ifdef NO_CNF_IMAGE
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`else
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2'b11 :
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begin
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calc_target_abort <= 1'b1 ;
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end
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`endif
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`else
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2'b11 :
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begin
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calc_target_abort <= 1'b1 ;
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end
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`endif
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default :
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begin
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calc_target_abort <= 1'b0 ;
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calc_target_abort <= 1'b0 ;
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end
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end
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endcase
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end
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// WRITE COMMANDS
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// WRITE COMMANDS
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`BC_IO_WRITE :
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`BC_IO_WRITE :
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begin
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begin
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case ({hit0_in, hit0_conf})
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case ({hit0_in, hit0_conf})
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`ifdef HOST
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`ifdef HOST
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`ifdef NO_CNF_IMAGE
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`ifdef NO_CNF_IMAGE
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`else
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`else
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2'b11 :
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2'b11 :
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begin
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begin
|
calc_target_abort <= 1'b1 ;
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calc_target_abort <= 1'b0 ;
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end
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end
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`endif
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`endif
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`else
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`else
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2'b11 :
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2'b11 :
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begin
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begin
|
calc_target_abort <= 1'b1 ;
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calc_target_abort <= 1'b0 ;
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end
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end
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`endif
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`endif
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default :
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default :
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begin
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begin
|
if (io_be_ok)
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if (io_be_ok)
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| Line 856... |
Line 840... |
end
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end
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endcase
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endcase
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end
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end
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`BC_MEM_WRITE_INVAL :
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`BC_MEM_WRITE_INVAL :
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begin
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begin
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case ({hit0_in, hit0_conf})
|
|
`ifdef HOST
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|
`ifdef NO_CNF_IMAGE
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`else
|
|
2'b11 :
|
|
begin
|
|
calc_target_abort <= 1'b1 ;
|
|
end
|
|
`endif
|
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`else
|
|
2'b11 :
|
|
begin
|
|
calc_target_abort <= 1'b1 ;
|
|
end
|
|
`endif
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|
default :
|
|
begin
|
|
calc_target_abort <= 1'b0 ;
|
calc_target_abort <= 1'b0 ;
|
end
|
end
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endcase
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|
end
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default :
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default :
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begin
|
begin
|
calc_target_abort <= 1'b0 ;
|
calc_target_abort <= 1'b0 ;
|
end
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end
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endcase
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endcase
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