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Line 40... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2002/02/19 16:32:37 mihad
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// Modified testbench and fixed some bugs
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//
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// Revision 1.3 2002/02/01 15:25:12 mihad
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// Revision 1.3 2002/02/01 15:25:12 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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// Repaired a few bugs, updated specification, added test bench files and design document
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//
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//
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// Revision 1.2 2001/10/05 08:14:30 mihad
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// Revision 1.2 2001/10/05 08:14:30 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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// Updated all files with inclusion of timescale file for simulation purposes.
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Line 702... |
assign same_read_out = (same_read_request) ; // && ~pcir_fifo_empty_in) ;
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assign same_read_out = (same_read_request) ; // && ~pcir_fifo_empty_in) ;
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// Signals for byte enable checking
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// Signals for byte enable checking
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reg addr_burst_ok ;
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reg addr_burst_ok ;
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reg io_be_ok ;
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reg io_be_ok ;
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reg conf_be_ok ;
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// Byte enable checking for IO, MEMORY and CONFIGURATION spaces - be_in is active low!
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// Byte enable checking for IO, MEMORY and CONFIGURATION spaces - be_in is active low!
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always@(strd_address or be_in)
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always@(strd_address or be_in)
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begin
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begin
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case (strd_address[1:0])
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case (strd_address[1:0])
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2'b11 :
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2'b11 :
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begin
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begin
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addr_burst_ok <= 1'b0 ;
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addr_burst_ok <= 1'b0 ;
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io_be_ok <= (be_in[2] && be_in[1] && be_in[0]) ; // only be3 can be active
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io_be_ok <= (be_in[2] && be_in[1] && be_in[0]) ; // only be3 can be active
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conf_be_ok <= 1'b0 ;
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end
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end
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2'b10 :
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2'b10 :
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begin
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begin
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addr_burst_ok <= 1'b0 ;
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addr_burst_ok <= 1'b0 ;
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io_be_ok <= (~be_in[2] && be_in[1] && be_in[0]) || (be_in[3] && be_in[2] && be_in[1] && be_in[0]) ;
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io_be_ok <= (~be_in[2] && be_in[1] && be_in[0]) || (be_in[3] && be_in[2] && be_in[1] && be_in[0]) ;
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conf_be_ok <= 1'b0 ;
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end
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end
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2'b01 :
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2'b01 :
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begin
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begin
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addr_burst_ok <= 1'b0 ;
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addr_burst_ok <= 1'b0 ;
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io_be_ok <= (~be_in[1] && be_in[0]) || (be_in[3] && be_in[2] && be_in[1] && be_in[0]) ;
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io_be_ok <= (~be_in[1] && be_in[0]) || (be_in[3] && be_in[2] && be_in[1] && be_in[0]) ;
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conf_be_ok <= 1'b0 ;
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end
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end
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default : // 2'b00
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default : // 2'b00
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begin
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begin
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addr_burst_ok <= 1'b1 ;
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addr_burst_ok <= 1'b1 ;
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io_be_ok <= (~be_in[0]) || (be_in[3] && be_in[2] && be_in[1] && be_in[0]) ;
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io_be_ok <= (~be_in[0]) || (be_in[3] && be_in[2] && be_in[1] && be_in[0]) ;
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conf_be_ok <= 1'b1 ;
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end
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end
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endcase
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endcase
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end
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end
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reg calc_target_abort ;
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wire calc_target_abort = (norm_bc[3:1] == `BC_IO_RW) ? !io_be_ok : 1'b0 ;
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// Target abort indication regarding the registered bus command and current signals for byte enable checking
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always@(norm_bc or hit0_in or io_be_ok or conf_be_ok)
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begin
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case (norm_bc)
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// READ COMMANDS
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`BC_IO_READ :
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begin
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case ({hit0_in, hit0_conf})
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`ifdef HOST
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`ifdef NO_CNF_IMAGE
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`else
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2'b11 :
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begin
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calc_target_abort <= 1'b0 ;
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end
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`endif
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`else
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2'b11 :
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begin
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calc_target_abort <= 1'b0 ;
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end
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`endif
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default :
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begin
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if (io_be_ok)
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begin
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calc_target_abort <= 1'b0 ;
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end
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else
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begin
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calc_target_abort <= 1'b1 ;
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end
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end
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endcase
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end
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`BC_MEM_READ :
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begin
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calc_target_abort <= 1'b0 ;
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end
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`BC_CONF_READ :
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begin
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case (conf_be_ok)
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1'b1 :
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begin
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calc_target_abort <= 1'b0 ;
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end
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default :
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begin
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calc_target_abort <= 1'b1 ;
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end
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endcase
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end
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`BC_MEM_READ_LN,
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`BC_MEM_READ_MUL :
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begin
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calc_target_abort <= 1'b0 ;
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end
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// WRITE COMMANDS
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`BC_IO_WRITE :
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begin
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case ({hit0_in, hit0_conf})
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`ifdef HOST
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`ifdef NO_CNF_IMAGE
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`else
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2'b11 :
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begin
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calc_target_abort <= 1'b0 ;
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end
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`endif
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`else
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2'b11 :
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begin
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calc_target_abort <= 1'b0 ;
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end
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`endif
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default :
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begin
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if (io_be_ok)
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begin
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calc_target_abort <= 1'b0 ;
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end
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else
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begin
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calc_target_abort <= 1'b1 ;
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end
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end
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endcase
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end
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`BC_MEM_WRITE :
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begin
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calc_target_abort <= 1'b0 ;
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end
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`BC_CONF_WRITE :
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begin
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case (conf_be_ok)
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1'b1 :
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begin
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calc_target_abort <= 1'b0 ;
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end
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default :
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begin
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calc_target_abort <= 1'b1 ;
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end
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endcase
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end
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`BC_MEM_WRITE_INVAL :
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begin
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calc_target_abort <= 1'b0 ;
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end
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default :
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begin
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calc_target_abort <= 1'b0 ;
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end
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endcase
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end
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wire [3:0] pcir_fifo_control_input = pcir_fifo_empty_in ? 4'h0 : pcir_fifo_control_in ;
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wire [3:0] pcir_fifo_control_input = pcir_fifo_empty_in ? 4'h0 : pcir_fifo_control_in ;
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// Medium registers for data and control busses from PCIR_FIFO
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// Medium registers for data and control busses from PCIR_FIFO
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reg [31:0] pcir_fifo_data_reg ;
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reg [31:0] pcir_fifo_data_reg ;
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