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Line 40... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.9 2003/01/27 16:49:31 mihad
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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//
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// Revision 1.8 2003/01/21 16:06:56 mihad
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// Revision 1.8 2003/01/21 16:06:56 mihad
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// Bug fixes, testcases added.
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// Bug fixes, testcases added.
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//
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//
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// Revision 1.7 2002/09/24 19:09:17 mihad
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// Revision 1.7 2002/09/24 19:09:17 mihad
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// Number of state bits define was removed
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// Number of state bits define was removed
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| Line 98... |
Line 101... |
// address, data, bus command, byte enable in/outs
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// address, data, bus command, byte enable in/outs
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pci_ad_reg_in,
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pci_ad_reg_in,
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pci_ad_out,
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pci_ad_out,
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pci_ad_en_out,
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pci_ad_en_out,
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pci_cbe_reg_in,
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pci_cbe_reg_in,
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pci_cbe_in,
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bckp_trdy_en_in,
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bckp_trdy_en_in,
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bckp_devsel_in,
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bckp_devsel_in,
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bckp_trdy_in,
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bckp_trdy_in,
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bckp_stop_in,
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bckp_stop_in,
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pci_trdy_reg_in,
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pci_trdy_reg_in,
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| Line 113... |
Line 117... |
bc_out,
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bc_out,
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bc0_out,
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bc0_out,
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data_out,
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data_out,
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data_in,
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data_in,
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be_out,
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be_out,
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next_be_out,
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req_out,
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req_out,
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rdy_out,
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rdy_out,
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addr_phase_out,
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addr_phase_out,
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bckp_devsel_out,
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bckp_devsel_out,
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bckp_trdy_out,
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bckp_trdy_out,
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| Line 186... |
Line 191... |
// address, data, bus command, byte enable in/outs
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// address, data, bus command, byte enable in/outs
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input [31:0] pci_ad_reg_in ;
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input [31:0] pci_ad_reg_in ;
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output [31:0] pci_ad_out ;
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output [31:0] pci_ad_out ;
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output pci_ad_en_out ;
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output pci_ad_en_out ;
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input [3:0] pci_cbe_reg_in ;
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input [3:0] pci_cbe_reg_in ;
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input [3:0] pci_cbe_in ;
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input bckp_trdy_en_in ;
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input bckp_trdy_en_in ;
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input bckp_devsel_in ;
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input bckp_devsel_in ;
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input bckp_trdy_in ;
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input bckp_trdy_in ;
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input bckp_stop_in ;
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input bckp_stop_in ;
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input pci_trdy_reg_in ;
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input pci_trdy_reg_in ;
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Line 211... |
output [3:0] bc_out ; // current request bus command output - registered
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output [3:0] bc_out ; // current request bus command output - registered
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output bc0_out ; // current cycle RW signal output
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output bc0_out ; // current cycle RW signal output
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input [31:0] data_in ; // for read operations - current dataphase data input
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input [31:0] data_in ; // for read operations - current dataphase data input
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output [31:0] data_out ; // for write operations - current request data output - registered
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output [31:0] data_out ; // for write operations - current request data output - registered
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output [3:0] be_out ; // current dataphase byte enable outputs - registered
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output [3:0] be_out ; // current dataphase byte enable outputs - registered
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output [3:0] next_be_out ; // next dataphase byte enable outputs - NOT registered
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// Port connection control signals from PCI FSM
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// Port connection control signals from PCI FSM
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output req_out ; // Read is requested to WB master
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output req_out ; // Read is requested to WB master
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output rdy_out ; // DATA / ADDRESS selection when read or write - registered
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output rdy_out ; // DATA / ADDRESS selection when read or write - registered
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output addr_phase_out ; // Indicates address phase and also fast-back-to-back address phase - registered
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output addr_phase_out ; // Indicates address phase and also fast-back-to-back address phase - registered
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output bckp_devsel_out ; // DEVSEL output (which is registered) equivalent
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output bckp_devsel_out ; // DEVSEL output (which is registered) equivalent
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Line 531... |
// if not disconnect without data and not target abort (only during reads)
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// if not disconnect without data and not target abort (only during reads)
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// MUST BE ANDED WITH CRITICAL ~FRAME
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// MUST BE ANDED WITH CRITICAL ~FRAME
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wire trdy_w_frm = (
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wire trdy_w_frm = (
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(state_transfere && !cnf_progress && !norm_access_to_conf_reg && rw_cbe0 && !disconect_wo_data) ||
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(state_transfere && !cnf_progress && !norm_access_to_conf_reg && rw_cbe0 && !disconect_wo_data) ||
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(state_transfere && !cnf_progress && !norm_access_to_conf_reg && ~rw_cbe0 && !disconect_wo_data && ~pcir_fifo_data_err_in) ||
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(state_transfere && !cnf_progress && !norm_access_to_conf_reg && ~rw_cbe0 && !disconect_wo_data && ~pcir_fifo_data_err_in) ||
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(state_transfere && !cnf_progress && !norm_access_to_conf_reg && disconect_w_data && pci_irdy_reg_in && (!rw_cbe0 && !pcir_fifo_data_err_in))
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(state_transfere && !cnf_progress && !norm_access_to_conf_reg && disconect_w_data && pci_irdy_reg_in &&
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((~rw_cbe0 && ~pcir_fifo_data_err_in) || rw_cbe0))
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) ;
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) ;
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// if not disconnect without data and not target abort (only during reads)
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// if not disconnect without data and not target abort (only during reads)
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// MUST BE ANDED WITH CRITICAL ~FRAME AND IRDY
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// MUST BE ANDED WITH CRITICAL ~FRAME AND IRDY
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wire trdy_w_frm_irdy = ( ~bckp_trdy_in ) ;
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wire trdy_w_frm_irdy = ( ~bckp_trdy_in ) ;
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// TRDY critical module used for preserving the architecture because of minimum delay for critical inputs
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// TRDY critical module used for preserving the architecture because of minimum delay for critical inputs
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| Line 736... |
Line 744... |
// data and address outputs assignments!
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// data and address outputs assignments!
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assign pci_ad_out = data_in ;
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assign pci_ad_out = data_in ;
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assign data_out = pci_ad_reg_in ;
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assign data_out = pci_ad_reg_in ;
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assign be_out = pci_cbe_reg_in ;
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assign be_out = pci_cbe_reg_in ;
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assign next_be_out = pci_cbe_in ;
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assign address_out = pci_ad_reg_in ;
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assign address_out = pci_ad_reg_in ;
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assign bc_out = pci_cbe_reg_in ;
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assign bc_out = pci_cbe_reg_in ;
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assign bc0_out = rw_cbe0 ;
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assign bc0_out = rw_cbe0 ;
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