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[/] [pci/] [tags/] [rel_7/] [rtl/] [verilog/] [pci_target32_sm.v] - Diff between revs 73 and 77

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Rev 73 Rev 77
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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.8  2003/01/21 16:06:56  mihad
 
// Bug fixes, testcases added.
 
//
// Revision 1.7  2002/09/24 19:09:17  mihad
// Revision 1.7  2002/09/24 19:09:17  mihad
// Number of state bits define was removed
// Number of state bits define was removed
//
//
// Revision 1.6  2002/09/24 18:30:00  mihad
// Revision 1.6  2002/09/24 18:30:00  mihad
// Changed state machine encoding to true one-hot
// Changed state machine encoding to true one-hot
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// synopsys translate_off
// synopsys translate_off
`include "timescale.v"
`include "timescale.v"
// synopsys translate_on
// synopsys translate_on
 
 
module PCI_TARGET32_SM
module pci_target32_sm
(
(
    // system inputs
    // system inputs
    clk_in,
    clk_in,
    reset_in,
    reset_in,
    // master inputs
    // master inputs
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                              backoff ;
                              backoff ;
end
end
assign config_disconnect = sm_transfere && (norm_access_to_conf_reg || cnf_progress) ;
assign config_disconnect = sm_transfere && (norm_access_to_conf_reg || cnf_progress) ;
 
 
// Clock enable module used for preserving the architecture because of minimum delay for critical inputs
// Clock enable module used for preserving the architecture because of minimum delay for critical inputs
PCI_TARGET32_CLK_EN         pci_target_clock_en
pci_target32_clk_en pci_target_clock_en
(
(
    .addr_phase             (addr_phase),
    .addr_phase             (addr_phase),
    .config_access          (config_access),
    .config_access          (config_access),
    .addr_claim_in          (addr_claim_in),
    .addr_claim_in          (addr_claim_in),
    .pci_frame_in           (pci_frame_in),
    .pci_frame_in           (pci_frame_in),
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                            ) ;
                            ) ;
        // if not disconnect without data and not target abort (only during reads)
        // if not disconnect without data and not target abort (only during reads)
        // MUST BE ANDED WITH CRITICAL ~FRAME AND IRDY
        // MUST BE ANDED WITH CRITICAL ~FRAME AND IRDY
wire    trdy_w_frm_irdy =   ( ~bckp_trdy_in ) ;
wire    trdy_w_frm_irdy =   ( ~bckp_trdy_in ) ;
// TRDY critical module used for preserving the architecture because of minimum delay for critical inputs
// TRDY critical module used for preserving the architecture because of minimum delay for critical inputs
PCI_TARGET32_TRDY_CRIT      pci_target_trdy_critical
pci_target32_trdy_crit pci_target_trdy_critical
(
(
    .trdy_w                 (trdy_w),
    .trdy_w                 (trdy_w),
    .trdy_w_frm             (trdy_w_frm),
    .trdy_w_frm             (trdy_w_frm),
    .trdy_w_frm_irdy        (trdy_w_frm_irdy),
    .trdy_w_frm_irdy        (trdy_w_frm_irdy),
    .pci_frame_in           (pci_frame_in),
    .pci_frame_in           (pci_frame_in),
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wire    stop_w_frm_irdy =   (
wire    stop_w_frm_irdy =   (
        (state_transfere && (disconect_wo_data)) ||
        (state_transfere && (disconect_wo_data)) ||
        (state_transfere && ~rw_cbe0 && pcir_fifo_data_err_in)
        (state_transfere && ~rw_cbe0 && pcir_fifo_data_err_in)
                            ) ;
                            ) ;
// STOP critical module used for preserving the architecture because of minimum delay for critical inputs
// STOP critical module used for preserving the architecture because of minimum delay for critical inputs
PCI_TARGET32_STOP_CRIT      pci_target_stop_critical
pci_target32_stop_crit pci_target_stop_critical
(
(
    .stop_w                 (stop_w),
    .stop_w                 (stop_w),
    .stop_w_frm             (stop_w_frm),
    .stop_w_frm             (stop_w_frm),
    .stop_w_frm_irdy        (stop_w_frm_irdy),
    .stop_w_frm_irdy        (stop_w_frm_irdy),
    .pci_frame_in           (pci_frame_in),
    .pci_frame_in           (pci_frame_in),
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        // MUST BE ANDED WITH CRITICAL ~FRAME AND IRDY
        // MUST BE ANDED WITH CRITICAL ~FRAME AND IRDY
wire    devs_w_frm_irdy =   (
wire    devs_w_frm_irdy =   (
        (state_transfere && ~rw_cbe0 && pcir_fifo_data_err_in)
        (state_transfere && ~rw_cbe0 && pcir_fifo_data_err_in)
                            ) ;
                            ) ;
// DEVSEL critical module used for preserving the architecture because of minimum delay for critical inputs
// DEVSEL critical module used for preserving the architecture because of minimum delay for critical inputs
PCI_TARGET32_DEVS_CRIT      pci_target_devsel_critical
pci_target32_devs_crit pci_target_devsel_critical
(
(
    .devs_w                 (devs_w),
    .devs_w                 (devs_w),
    .devs_w_frm             (devs_w_frm),
    .devs_w_frm             (devs_w_frm),
    .devs_w_frm_irdy        (devs_w_frm_irdy),
    .devs_w_frm_irdy        (devs_w_frm_irdy),
    .pci_frame_in           (pci_frame_in),
    .pci_frame_in           (pci_frame_in),

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