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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2003/01/27 16:49:31 mihad
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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//
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// Revision 1.7 2002/12/05 12:19:23 mihad
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// Revision 1.7 2002/12/05 12:19:23 mihad
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// *** empty log message ***
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// *** empty log message ***
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//
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//
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// Revision 1.6 2002/10/11 14:15:29 mihad
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// Revision 1.6 2002/10/11 14:15:29 mihad
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// Cleaned up non-blocking assignments in combinatinal logic statements
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// Cleaned up non-blocking assignments in combinatinal logic statements
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`endif
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`endif
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// wire for read attempt - 1 when PCI Target is attempting a read and PCIR_FIFO is not full !
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// wire for read attempt - 1 when PCI Target is attempting a read and PCIR_FIFO is not full !
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// because of transaction ordering, PCI Master must not start read untill all writes are done -> at that
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// because of transaction ordering, PCI Master must not start read untill all writes are done -> at that
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// moment PCIW_FIFO is empty !!! (when read is pending PCI Target will block new reads and writes)
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// moment PCIW_FIFO is empty !!! (when read is pending PCI Target will block new reads and writes)
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wire r_attempt = ( pci_tar_read_request && !w_attempt);// pciw_fifo_empty_in ) ;
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wire r_attempt = ( pci_tar_read_request && !w_attempt && pciw_fifo_empty_in ) ;
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// Signal is used for reads on WB, when there is retry!
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// Signal is used for reads on WB, when there is retry!
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reg first_wb_data_access ;
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reg first_wb_data_access ;
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reg last_data_from_pciw_fifo ; // signal tells when there is last data in pciw_fifo
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reg last_data_from_pciw_fifo ; // signal tells when there is last data in pciw_fifo
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