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Line 40... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2003/07/29 08:20:11 mihad
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// Found and simulated the problem in the synchronization logic.
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// Repaired the synchronization logic in the FIFOs.
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//
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// Revision 1.2 2003/03/26 13:16:18 mihad
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// Revision 1.2 2003/03/26 13:16:18 mihad
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// Added the reset value parameter to the synchronizer flop module.
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// Added the reset value parameter to the synchronizer flop module.
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// Added resets to all synchronizer flop instances.
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// Added resets to all synchronizer flop instances.
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// Repaired initial sync value in fifos.
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// Repaired initial sync value in fifos.
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//
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//
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Line 245... |
Gray coded write address pointer is synchronized to read clock domain and compared to Gray coded read address pointer.
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Gray coded write address pointer is synchronized to read clock domain and compared to Gray coded read address pointer.
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If they are equal, fifo is empty.
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If they are equal, fifo is empty.
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--------------------------------------------------------------------------------------------------------------------------------*/
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--------------------------------------------------------------------------------------------------------------------------------*/
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wire [(ADDR_LENGTH - 1):0] rclk_sync_wgrey_addr ;
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wire [(ADDR_LENGTH - 1):0] rclk_sync_wgrey_addr ;
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reg [(ADDR_LENGTH - 1):0] rclk_wgrey_addr ;
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reg [(ADDR_LENGTH - 1):0] rclk_wgrey_addr ;
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synchronizer_flop #(ADDR_LENGTH, 0) i_synchronizer_reg_wgrey_addr
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pci_synchronizer_flop #(ADDR_LENGTH, 0) i_synchronizer_reg_wgrey_addr
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(
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(
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.data_in (wgrey_addr),
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.data_in (wgrey_addr),
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.clk_out (rclock_in),
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.clk_out (rclock_in),
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.sync_data_out (rclk_sync_wgrey_addr),
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.sync_data_out (rclk_sync_wgrey_addr),
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.async_reset (clear)
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.async_reset (clear)
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