| Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2003/03/26 13:16:18 mihad
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// Added the reset value parameter to the synchronizer flop module.
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// Added resets to all synchronizer flop instances.
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// Repaired initial sync value in fifos.
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//
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// Revision 1.1 2003/01/27 16:49:31 mihad
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// Revision 1.1 2003/01/27 16:49:31 mihad
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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//
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//
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// Revision 1.6 2002/11/27 20:36:13 mihad
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// Revision 1.6 2002/11/27 20:36:13 mihad
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// Changed the code a bit to make it more readable.
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// Changed the code a bit to make it more readable.
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| Line 79... |
Line 84... |
rclock_in,
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rclock_in,
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wclock_in,
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wclock_in,
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renable_in,
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renable_in,
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wenable_in,
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wenable_in,
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reset_in,
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reset_in,
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// flush_in, // not used
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almost_full_out,
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almost_full_out,
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full_out,
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full_out,
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empty_out,
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empty_out,
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waddr_out,
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waddr_out,
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raddr_out,
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raddr_out,
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| Line 124... |
Line 128... |
// write address register
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// write address register
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reg [(ADDR_LENGTH - 1):0] waddr;
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reg [(ADDR_LENGTH - 1):0] waddr;
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assign waddr_out = waddr ;
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assign waddr_out = waddr ;
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// grey code registers
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// grey code registers
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reg [(ADDR_LENGTH - 1):0] wgrey_addr ; // current
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// grey code register for next write address
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// grey code register for next write address
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reg [(ADDR_LENGTH - 1):0] wgrey_next ; // next
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reg [(ADDR_LENGTH - 1):0] wgrey_next ; // next
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// next write gray address calculation - bitwise xor between address and shifted address
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// next write gray address calculation - bitwise xor between address and shifted address
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wire [(ADDR_LENGTH - 2):0] calc_wgrey_next = waddr[(ADDR_LENGTH - 1):1] ^ waddr[(ADDR_LENGTH - 2):0] ;
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wire [(ADDR_LENGTH - 2):0] calc_wgrey_next = waddr[(ADDR_LENGTH - 1):1] ^ waddr[(ADDR_LENGTH - 2):0] ;
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| Line 138... |
Line 143... |
reg [(ADDR_LENGTH - 1):0] rgrey_next ; // next
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reg [(ADDR_LENGTH - 1):0] rgrey_next ; // next
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// next read gray address calculation - bitwise xor between address and shifted address
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// next read gray address calculation - bitwise xor between address and shifted address
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wire [(ADDR_LENGTH - 2):0] calc_rgrey_next = raddr[(ADDR_LENGTH - 1):1] ^ raddr[(ADDR_LENGTH - 2):0] ;
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wire [(ADDR_LENGTH - 2):0] calc_rgrey_next = raddr[(ADDR_LENGTH - 1):1] ^ raddr[(ADDR_LENGTH - 2):0] ;
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// FFs for registered empty and full flags
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wire empty ;
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wire full ;
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// almost_full tag
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wire almost_full ;
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// write allow wire - writes are allowed when fifo is not full
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// write allow wire - writes are allowed when fifo is not full
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wire wallow = wenable_in && !full ;
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assign wallow_out = wenable_in & ~full_out ;
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// write allow output assignment
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assign wallow_out = wallow && !full ;
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// read allow wire
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wire rallow ;
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// full output assignment
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assign full_out = full ;
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// almost full output assignment
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assign almost_full_out = almost_full && !full ;
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// clear generation for FFs and registers
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// clear generation for FFs and registers
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wire clear = reset_in /*|| flush_in*/ ; // flush not used
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wire clear = reset_in ;
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assign empty_out = empty ;
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//rallow generation
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//rallow generation
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assign rallow = renable_in && !empty ; // reads allowed if read enable is high and FIFO is not empty
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assign rallow_out = renable_in & ~empty_out ; // reads allowed if read enable is high and FIFO is not empty
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// rallow output assignment
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assign rallow_out = rallow ;
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// at any clock edge that rallow is high, this register provides next read address, so wait cycles are not necessary
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// at any clock edge that rallow is high, this register provides next read address, so wait cycles are not necessary
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// when FIFO is empty, this register provides actual read address, so first location can be read
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// when FIFO is empty, this register provides actual read address, so first location can be read
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reg [(ADDR_LENGTH - 1):0] raddr_plus_one ;
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reg [(ADDR_LENGTH - 1):0] raddr_plus_one ;
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// address output mux - when FIFO is empty, current actual address is driven out, when it is non - empty next address is driven out
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// address output mux - when FIFO is empty, current actual address is driven out, when it is non - empty next address is driven out
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// done for zero wait state burst
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// done for zero wait state burst
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assign raddr_out = rallow ? raddr_plus_one : raddr ;
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assign raddr_out = rallow_out ? raddr_plus_one : raddr ;
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always@(posedge rclock_in or posedge clear)
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always@(posedge rclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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begin
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begin
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raddr_plus_one <= #`FF_DELAY 4 ;
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raddr_plus_one <= #`FF_DELAY 4 ;
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raddr <= #`FF_DELAY 3 ;
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raddr <= #`FF_DELAY 3 ;
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end
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end
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else if (rallow)
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else if (rallow_out)
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begin
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begin
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raddr_plus_one <= #`FF_DELAY raddr_plus_one + 1'b1 ;
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raddr_plus_one <= #`FF_DELAY raddr_plus_one + 1'b1 ;
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raddr <= #`FF_DELAY raddr_plus_one ;
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raddr <= #`FF_DELAY raddr_plus_one ;
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end
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end
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end
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end
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| Line 206... |
Line 187... |
always@(posedge rclock_in or posedge clear)
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always@(posedge rclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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begin
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begin
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// initial value is 0
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// initial value is 0
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rgrey_minus1 <= #`FF_DELAY 0 ;
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rgrey_minus1 <= #1 0 ;
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rgrey_addr <= #`FF_DELAY 1 ;
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rgrey_addr <= #1 1 ;
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rgrey_next <= #`FF_DELAY 3 ;
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rgrey_next <= #`FF_DELAY 3 ;
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end
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end
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else
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else
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if (rallow)
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if (rallow_out)
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begin
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begin
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rgrey_minus1 <= #`FF_DELAY rgrey_addr ;
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rgrey_minus1 <= #1 rgrey_addr ;
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rgrey_addr <= #`FF_DELAY rgrey_next ;
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rgrey_addr <= #1 rgrey_next ;
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rgrey_next <= #`FF_DELAY {raddr[ADDR_LENGTH - 1], calc_rgrey_next} ;
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rgrey_next <= #`FF_DELAY {raddr[ADDR_LENGTH - 1], calc_rgrey_next} ;
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end
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end
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end
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end
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/*--------------------------------------------------------------------------------------------
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/*--------------------------------------------------------------------------------------------
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| Line 227... |
Line 208... |
// grey coded address pipeline for status generation in write clock domain
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// grey coded address pipeline for status generation in write clock domain
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always@(posedge wclock_in or posedge clear)
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always@(posedge wclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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begin
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begin
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wgrey_next <= #`FF_DELAY 3 ;
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wgrey_addr <= #`FF_DELAY 1 ;
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wgrey_next <= #1 3 ;
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end
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end
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else
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else
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if (wallow)
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if (wallow_out)
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begin
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begin
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wgrey_next <= #`FF_DELAY {waddr[(ADDR_LENGTH - 1)], calc_wgrey_next} ;
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wgrey_addr <= #`FF_DELAY wgrey_next ;
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wgrey_next <= #1 {waddr[(ADDR_LENGTH - 1)], calc_wgrey_next} ;
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end
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end
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end
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end
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// write address counter - nothing special - initial value is important though
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// write address counter - nothing special - initial value is important though
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always@(posedge wclock_in or posedge clear)
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always@(posedge wclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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// initial value 4
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// initial value 4
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waddr <= #`FF_DELAY 3 ;
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waddr <= #`FF_DELAY 3 ;
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else
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else
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if (wallow)
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if (wallow_out)
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waddr <= #`FF_DELAY waddr + 1'b1 ;
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waddr <= #`FF_DELAY waddr + 1'b1 ;
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end
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end
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/*------------------------------------------------------------------------------------------------------------------------------
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/*------------------------------------------------------------------------------------------------------------------------------
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Full control:
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Gray coded address of read address decremented by 1 is synchronized to write clock domain and compared to:
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Gray coded read address pointer is synchronized to write clock domain and compared to Gray coded next write address.
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If they are equal, fifo is full.
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- Gray coded write address. If they are equal, fifo is full.
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Almost full control:
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- Gray coded next write address. If they are equal, fifo is almost full.
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Gray coded address of read address decremented by 1 is synchronized to write clock domain and compared to Gray coded next write
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address. If they are equal, fifo is almost full.
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--------------------------------------------------------------------------------------------------------------------------------*/
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--------------------------------------------------------------------------------------------------------------------------------*/
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wire [(ADDR_LENGTH - 1):0] wclk_sync_rgrey_addr ;
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reg [(ADDR_LENGTH - 1):0] wclk_rgrey_addr ;
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wire [(ADDR_LENGTH - 1):0] wclk_sync_rgrey_minus1 ;
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wire [(ADDR_LENGTH - 1):0] wclk_sync_rgrey_minus1 ;
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reg [(ADDR_LENGTH - 1):0] wclk_rgrey_minus1 ;
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reg [(ADDR_LENGTH - 1):0] wclk_rgrey_minus1 ;
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synchronizer_flop #(ADDR_LENGTH, 1) i_synchronizer_reg_rgrey_addr
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(
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.data_in (rgrey_addr),
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.clk_out (wclock_in),
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.sync_data_out (wclk_sync_rgrey_addr),
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.async_reset (clear)
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) ;
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synchronizer_flop #(ADDR_LENGTH, 0) i_synchronizer_reg_rgrey_minus1
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synchronizer_flop #(ADDR_LENGTH, 0) i_synchronizer_reg_rgrey_minus1
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(
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(
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.data_in (rgrey_minus1),
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.data_in (rgrey_minus1),
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.clk_out (wclock_in),
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.clk_out (wclock_in),
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.sync_data_out (wclk_sync_rgrey_minus1),
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.sync_data_out (wclk_sync_rgrey_minus1),
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| Line 281... |
Line 252... |
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always@(posedge wclock_in or posedge clear)
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always@(posedge wclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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begin
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begin
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wclk_rgrey_addr <= #`FF_DELAY 1 ;
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wclk_rgrey_minus1 <= #`FF_DELAY 0 ;
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wclk_rgrey_minus1 <= #`FF_DELAY 0 ;
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end
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end
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else
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else
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begin
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begin
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wclk_rgrey_addr <= #`FF_DELAY wclk_sync_rgrey_addr ;
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wclk_rgrey_minus1 <= #`FF_DELAY wclk_sync_rgrey_minus1 ;
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wclk_rgrey_minus1 <= #`FF_DELAY wclk_sync_rgrey_minus1 ;
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end
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end
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end
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end
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assign full = (wgrey_next == wclk_rgrey_addr) ;
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assign full_out = (wgrey_addr == wclk_rgrey_minus1) ;
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assign almost_full = (wgrey_next == wclk_rgrey_minus1) ;
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assign almost_full_out = (wgrey_next == wclk_rgrey_minus1) ;
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/*------------------------------------------------------------------------------------------------------------------------------
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/*------------------------------------------------------------------------------------------------------------------------------
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Empty control:
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Empty control:
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Gray coded address of next write address is synchronized to read clock domain and compared to Gray coded next read address.
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Gray coded address of next write address is synchronized to read clock domain and compared to Gray coded next read address.
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If they are equal, fifo is empty.
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If they are equal, fifo is empty.
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| Line 317... |
Line 286... |
rclk_wgrey_next <= #`FF_DELAY 3 ;
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rclk_wgrey_next <= #`FF_DELAY 3 ;
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else
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else
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rclk_wgrey_next <= #`FF_DELAY rclk_sync_wgrey_next ;
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rclk_wgrey_next <= #`FF_DELAY rclk_sync_wgrey_next ;
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end
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end
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assign empty = (rgrey_next == rclk_wgrey_next) ;
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assign empty_out = (rgrey_next == rclk_wgrey_next) ;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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