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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1.1.1 2001/10/02 15:33:33 mihad
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// New project directory structure
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//
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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module ssvga_fifo(
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module ssvga_fifo(
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clk, crt_clk, rst, dat_i, wr_en, rd_en,
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clk, rst, dat_i, wr_en, rd_en,
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dat_o, full, empty, ssvga_en
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dat_o, full, empty, ssvga_en
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);
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);
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//
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//
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// I/O ports
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// I/O ports
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//
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//
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input clk; // Clock
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input clk; // Clock
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input crt_clk; // Clock for monitor
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input rst; // Reset
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input rst; // Reset
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input [31:0] dat_i; // Input data
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input [31:0] dat_i; // Input data
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input wr_en; // Write enable
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input wr_en; // Write enable
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input rd_en; // Read enable
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input rd_en; // Read enable
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output [7:0] dat_o; // Output data
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output [7:0] dat_o; // Output data
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reg [7:0] wr_ptr_plus1; // Write pointer
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reg [7:0] wr_ptr_plus1; // Write pointer
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reg [9:0] rd_ptr; // Read pointer
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reg [9:0] rd_ptr; // Read pointer
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reg [9:0] rd_ptr_plus1; // Read pointer plus1
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reg [9:0] rd_ptr_plus1; // Read pointer plus1
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wire rd_en_int; // FIFO internal read enable
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wire rd_en_int; // FIFO internal read enable
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wire [9:0] gray_rd_ptr; // gray code of read pointer
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wire [9:0] gray_wr_ptr; // gray code of write pointer
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wire [7:0] gray_wr_ptr_plus1;// gray code of write + 1 pointer
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reg [9:0] gray_read_ptr; // sinchronized gray read pointer on clk clock
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wire [9:0] sync_gray_rd_ptr; // intermediate sinc. of gray read pointer
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reg rd_ssvga_en; // sinchronized ssvga enable on crt_clk clock
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wire sync_ssvga_en; // intermediate sinc. of ssvga enable signal
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//
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//
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// Write pointer + 1
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// Write pointer + 1
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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Line 105... |
wr_ptr <= #1 wr_ptr_plus1 ;
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wr_ptr <= #1 wr_ptr_plus1 ;
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//
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//
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// Read pointer
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// Read pointer
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//
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//
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always @(posedge crt_clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst)
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if (rst)
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rd_ptr <= #1 10'b00_0000_0000;
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rd_ptr <= #1 10'b00_0000_0000;
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else if (~rd_ssvga_en)
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else if (~ssvga_en)
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rd_ptr <= #1 10'b00_0000_0000;
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rd_ptr <= #1 10'b00_0000_0000;
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else if (rd_en_int)
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else if (rd_en_int)
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rd_ptr <= #1 rd_ptr_plus1 ;
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rd_ptr <= #1 rd_ptr_plus1 ;
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always @(posedge crt_clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst)
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if (rst)
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rd_ptr_plus1 <= #1 10'b00_0000_0001;
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rd_ptr_plus1 <= #1 10'b00_0000_0001;
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else if (~rd_ssvga_en)
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else if (~ssvga_en)
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rd_ptr_plus1 <= #1 10'b00_0000_0001;
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rd_ptr_plus1 <= #1 10'b00_0000_0001;
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else if (rd_en_int)
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else if (rd_en_int)
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rd_ptr_plus1 <= #1 rd_ptr_plus1 + 1 ;
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rd_ptr_plus1 <= #1 rd_ptr_plus1 + 1 ;
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//
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//
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// Empty is asserted when both pointers match
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// Empty is asserted when both pointers match
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//
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//
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//assign empty = ( rd_ptr == {wr_ptr, 2'b00} ) ;
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assign empty = ( rd_ptr == {wr_ptr, 2'b00} ) ;
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assign empty = ( gray_wr_ptr == gray_read_ptr ) ;
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//
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//
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// Full is asserted when both pointers match
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// Full is asserted when both pointers match
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// and wr_ptr did increment in previous clock cycle
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// and wr_ptr did increment in previous clock cycle
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//
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//
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//assign full = ( wr_ptr_plus1 == rd_ptr[9:2] ) ;
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assign full = ( wr_ptr_plus1 == rd_ptr[9:2] ) ;
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assign full = ( gray_wr_ptr_plus1 == gray_read_ptr[9:2] ) ;
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wire valid_pix = 1'b1 ;
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wire valid_pix = 1'b1 ;
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//
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//
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// Read enable for FIFO
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// Read enable for FIFO
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Line 146... |
wire [7:0] dat_o_low ;
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wire [7:0] dat_o_low ;
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wire [7:0] dat_o_high ;
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wire [7:0] dat_o_high ;
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assign dat_o = rd_ptr[1] ? dat_o_high : dat_o_low ;
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assign dat_o = rd_ptr[1] ? dat_o_high : dat_o_low ;
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//#############################################################################
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// binary to gray converters for counter of different clock domain comparison
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assign gray_rd_ptr = (rd_ptr >> 1) ^ rd_ptr ;
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assign gray_wr_ptr = ({1'b0, wr_ptr, 1'b0}) ^ ({wr_ptr, 2'b00}) ;
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assign gray_wr_ptr_plus1 = (wr_ptr_plus1 >> 1) ^ wr_ptr_plus1 ;
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//#############################################################################
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// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
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synchronizer_flop #(10) read_ptr_sync
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(
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.data_in (gray_rd_ptr),
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.clk_out (clk),
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.sync_data_out (sync_gray_rd_ptr),
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.async_reset (rst)
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) ;
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always@(posedge clk or posedge rst)
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begin
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if (rst)
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gray_read_ptr <= #1 10'b0 ;
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else
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gray_read_ptr <= #1 sync_gray_rd_ptr ;
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end
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//##############################################################################
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// interemediate stage ssvga_en synchronization flip - flop - this one is prone to metastability
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synchronizer_flop ssvga_enable_sync
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(
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.data_in (ssvga_en),
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.clk_out (crt_clk),
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.sync_data_out (sync_ssvga_en),
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.async_reset (rst)
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) ;
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// crt side ssvga enable flip flop - gets a value from intermediate stage sync flip flop
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always@(posedge crt_clk or posedge rst)
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begin
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if (rst)
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rd_ssvga_en <= #1 1'b0 ;
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else
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rd_ssvga_en <= #1 sync_ssvga_en ;
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end
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RAMB4_S8_S16 ramb4_s8_0(
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RAMB4_S8_S16 ramb4_s8_0(
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.CLKA(crt_clk),
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.CLKA(clk),
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.RSTA(rst),
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.RSTA(rst),
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.ADDRA(ram_pix_address),
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.ADDRA(ram_pix_address),
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.DIA(8'h00),
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.DIA(8'h00),
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.ENA(1'b1),
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.ENA(1'b1),
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.WEA(1'b0),
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.WEA(1'b0),
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Line 165... |
.WEB(wr_en),
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.WEB(wr_en),
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.DOB()
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.DOB()
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);
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);
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RAMB4_S8_S16 ramb4_s8_1(
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RAMB4_S8_S16 ramb4_s8_1(
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.CLKA(crt_clk),
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.CLKA(clk),
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.RSTA(rst),
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.RSTA(rst),
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.ADDRA(ram_pix_address),
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.ADDRA(ram_pix_address),
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.DIA(8'h00),
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.DIA(8'h00),
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.ENA(1'b1),
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.ENA(1'b1),
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.WEA(1'b0),
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.WEA(1'b0),
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