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#-- Synplicity, Inc.
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#-- Synplicity, Inc.
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#-- Version Amplify 3.1
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#-- Version 7.2
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#-- Project file /shared/projects/pci/mihad/pci/apps/crt/syn/synplify/pci_crt.prj
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#-- Project file /shared/projects/pci/mihad/pci/apps/crt/syn/synplify/pci_crt.prj
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#-- Written on Fri Sep 27 16:20:50 2002
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#-- Written on Mon Mar 10 13:16:14 2003
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#add_file options
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#add_file options
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add_file -verilog "$LIB/xilinx/virtex.v"
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add_file -verilog "$LIB/xilinx/virtex.v"
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add_file -verilog "../../../../rtl/verilog/meta_flop.v"
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add_file -verilog "../../../../rtl/verilog/meta_flop.v"
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add_file -verilog "../../rtl/verilog/ssvga_wbm_if.v"
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add_file -verilog "../../rtl/verilog/ssvga_wbm_if.v"
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add_file -verilog "../../rtl/verilog/ssvga_wbs_if.v"
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add_file -verilog "../../rtl/verilog/ssvga_wbs_if.v"
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add_file -constraint "pci_crt.sdc"
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add_file -constraint "pci_crt.sdc"
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add_file -verilog "../../rtl/verilog/top.v"
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add_file -verilog "../../rtl/verilog/top.v"
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#reporting options
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#implementation: "rev_1"
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#implementation: "rev_1"
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impl -add rev_1
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impl -add rev_1
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#device options
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#device options
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set_option -package PQ208
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set_option -package PQ208
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set_option -speed_grade -5
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set_option -speed_grade -5
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#compilation/mapping options
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#compilation/mapping options
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set_option -default_enum_encoding default
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set_option -default_enum_encoding default
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set_option -symbolic_fsm_compiler 0
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set_option -symbolic_fsm_compiler 1
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set_option -resource_sharing 0
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set_option -resource_sharing 0
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set_option -use_fsm_explorer 0
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set_option -use_fsm_explorer 0
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#map options
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#map options
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set_option -frequency 50.000
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set_option -frequency 50.000
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set_option -fanout_limit 50
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set_option -fanout_limit 50
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set_option -disable_io_insertion 0
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set_option -disable_io_insertion 0
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set_option -pipe 0
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set_option -pipe 1
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set_option -fixgatedclocks 0
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set_option -retiming 1
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set_option -retiming 0
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set_option -modular 0
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set_option -modular 0
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set_option -update_models_cp 0
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set_option -verification_mode 0
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#simulation options
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#simulation options
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set_option -write_verilog 0
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set_option -write_verilog 0
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set_option -write_vhdl 0
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set_option -write_vhdl 0
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#set result format/file last
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#set result format/file last
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project -result_file "rev_1/top.edf"
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project -result_file "rev_1/top.edf"
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#implementation attributes
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#implementation attributes
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set_option -vlog_std v95
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set_option -compiler_compatible 0
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set_option -compiler_compatible 0
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set_option -random_floorplan 0
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set_option -random_floorplan 0
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set_option -include_path "../../rtl/verilog/;../../../../rtl/verilog/"
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set_option -popfeed 1
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set_option -constprop 1
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#netlist optimizer options
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set_option -createhierarchy 0
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set_option -enable_nfilter 0
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set_option -feedthrough 1
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set_option -constant_prop 1
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set_option -level_hierarchy 0
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#physical constraint options
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set_option -floorplan ""
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set_option -floorplan ""
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set_option -nfilter_user_path ""
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set_option -nfilter_user_path ""
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set_option -pin_assignment ""
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set_option -pin_assignment ""
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set_option -include_path "../../rtl/verilog/;../../../../rtl/verilog/"
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impl -active "rev_1"
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impl -active "rev_1"
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