Line 41... |
Line 41... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.6 2002/10/17 22:51:50 tadejm
|
|
// Changed BIST signals for RAMs.
|
|
//
|
// Revision 1.5 2002/10/11 10:09:01 mihad
|
// Revision 1.5 2002/10/11 10:09:01 mihad
|
// Added additional testcase and changed rst name in BIST to trst
|
// Added additional testcase and changed rst name in BIST to trst
|
//
|
//
|
// Revision 1.4 2002/10/08 17:17:05 mihad
|
// Revision 1.4 2002/10/08 17:17:05 mihad
|
// Added BIST signals for RAMs.
|
// Added BIST signals for RAMs.
|
Line 171... |
Line 174... |
// debug chain signals
|
// debug chain signals
|
scanb_rst, // bist scan reset
|
scanb_rst, // bist scan reset
|
scanb_clk, // bist scan clock
|
scanb_clk, // bist scan clock
|
scanb_si, // bist scan serial in
|
scanb_si, // bist scan serial in
|
scanb_so, // bist scan serial out
|
scanb_so, // bist scan serial out
|
scanb_sen // bist scan shift enable
|
scanb_en // bist scan shift enable
|
`endif
|
`endif
|
);
|
);
|
|
|
// WISHBONE system signals
|
// WISHBONE system signals
|
input CLK_I ;
|
input CLK_I ;
|
Line 277... |
Line 280... |
-----------------------------------------------------*/
|
-----------------------------------------------------*/
|
input scanb_rst; // bist scan reset
|
input scanb_rst; // bist scan reset
|
input scanb_clk; // bist scan clock
|
input scanb_clk; // bist scan clock
|
input scanb_si; // bist scan serial in
|
input scanb_si; // bist scan serial in
|
output scanb_so; // bist scan serial out
|
output scanb_so; // bist scan serial out
|
input scanb_sen; // bist scan shift enable
|
input scanb_en; // bist scan shift enable
|
|
|
// internal wires for serial chain connection
|
// internal wires for serial chain connection
|
wire SO_internal ;
|
wire SO_internal ;
|
wire SI_internal = SO_internal ;
|
wire SI_internal = SO_internal ;
|
`endif
|
`endif
|
Line 801... |
Line 804... |
,
|
,
|
.scanb_rst (scanb_rst),
|
.scanb_rst (scanb_rst),
|
.scanb_clk (scanb_clk),
|
.scanb_clk (scanb_clk),
|
.scanb_si (scanb_si),
|
.scanb_si (scanb_si),
|
.scanb_so (scanb_so),
|
.scanb_so (scanb_so),
|
.scanb_sen (scanb_sen)
|
.scanb_en (scanb_en)
|
`endif
|
`endif
|
);
|
);
|
|
|
// PCI TARGET UNIT INPUTS
|
// PCI TARGET UNIT INPUTS
|
wire [31:0] pciu_mdata_in = MDAT_I ;
|
wire [31:0] pciu_mdata_in = MDAT_I ;
|
Line 983... |
Line 986... |
,
|
,
|
.scanb_rst (scanb_rst),
|
.scanb_rst (scanb_rst),
|
.scanb_clk (scanb_clk),
|
.scanb_clk (scanb_clk),
|
.scanb_si (scanb_si),
|
.scanb_si (scanb_si),
|
.scanb_so (scanb_so),
|
.scanb_so (scanb_so),
|
.scanb_sen (scanb_sen)
|
.scanb_en (scanb_en)
|
`endif
|
`endif
|
);
|
);
|
|
|
|
|
// CONFIGURATION SPACE INPUTS
|
// CONFIGURATION SPACE INPUTS
|