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[/] [pci/] [tags/] [rel_8/] [rtl/] [verilog/] [pci_in_reg.v] - Diff between revs 21 and 77
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Rev 77 |
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/02/01 15:25:12 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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//
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// Revision 1.2 2001/10/05 08:14:29 mihad
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// Revision 1.2 2001/10/05 08:14:29 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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//
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// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
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// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
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// New project directory structure
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// New project directory structure
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "pci_constants.v"
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`include "pci_constants.v"
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// Module is used for registering PCI input signals
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// Module is used for registering PCI input signals
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// It provides data flip flops with reset
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// It provides data flip flops with reset
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module PCI_IN_REG
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module pci_in_reg
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(
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(
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reset_in,
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reset_in,
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clk_in,
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clk_in,
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pci_gnt_in,
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pci_gnt_in,
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pci_cbe_reg_out <= #`FF_DELAY pci_cbe_in ;
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pci_cbe_reg_out <= #`FF_DELAY pci_cbe_in ;
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end
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end
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end
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end
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endmodule
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endmodule
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