Back to project
URL
https://opencores.org/ocsvn/pci/pci/trunk
[/ ] [pci/ ] [tags/ ] [rel_8/ ] [rtl/ ] [verilog/ ] [pci_parity_check.v ] - Diff between revs 21 and 45
Go to most recent revision Show entire file Details Blame View Log
Rev 21
Rev 45
Line 40... Line 40...
////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////
// //
// CVS Revision History // CVS Revision History
// //
// $Log: not supported by cvs2svn $ // $Log: not supported by cvs2svn $
// Revision 1.3 2002/02/01 15:25:12 mihad
// Repaired a few bugs, updated specification, added test bench files and design document
//
// Revision 1.2 2001/10/05 08:14:30 mihad // Revision 1.2 2001/10/05 08:14:30 mihad
// Updated all files with inclusion of timescale file for simulation purposes. // Updated all files with inclusion of timescale file for simulation purposes.
// //
// Revision 1.1.1.1 2001/10/02 15:33:47 mihad // Revision 1.1.1.1 2001/10/02 15:33:47 mihad
// New project directory structure // New project directory structure
Line 295... Line 298...
else else
perr_sampled <= # `FF_DELAY perr_sampled_in ; perr_sampled <= # `FF_DELAY perr_sampled_in ;
end end
// assign output for parity error detected bit // assign output for parity error detected bit
assign par_err_detect_out = ~ pci_serr_out_in || ~ pci_perr_out_in || perr_sampled ; assign par_err_detect_out = ~ pci_serr_out_in || ~ pci_perr_out_in ; //|| perr_sampled ; MihaD - removed - detected parity error is set only during Master Reads or Target Writes
// FF indicating that that last operation was done as bus master // FF indicating that that last operation was done as bus master
reg frame_and_irdy_en_prev ; reg frame_and_irdy_en_prev ;
reg frame_and_irdy_en_prev_prev ; reg frame_and_irdy_en_prev_prev ;
reg master_perr_report ; reg master_perr_report ;
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.
