URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_9/] [bench/] [verilog/] [pci_bus_monitor.v] - Diff between revs 15 and 35

Rev 15	Rev 35
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`//===========================================================================`	`//===========================================================================`
`// $Id: pci_bus_monitor.v,v 1.1 2002-02-01 13:39:43 mihad Exp $`	`// $Id: pci_bus_monitor.v,v 1.2 2002-03-21 07:35:50 mihad Exp $`
`//`	`//`
`// Copyright 2001 Blue Beaver. All Rights Reserved.`	`// Copyright 2001 Blue Beaver. All Rights Reserved.`
`//`	`//`
`// Summary: Watch the PCI Bus Wires to try to see Protocol Errors.`	`// Summary: Watch the PCI Bus Wires to try to see Protocol Errors.`
`// This module also has access to the individual PCI Bus OE`	`// This module also has access to the individual PCI Bus OE`
Line 67...	Line 67...
`//`	`//`
`//===========================================================================`	`//===========================================================================`

`// Note that master aborts are the norm on Special Cycles!`	`// Note that master aborts are the norm on Special Cycles!`

`timescale 1ns/10ps	`// synopsys translate_off`
	`include "timescale.v"
	`// synopsys translate_on`
	//`timescale 1ns/10ps

`module pci_bus_monitor (`	`module pci_bus_monitor (`
`pci_ext_ad, pci_ext_cbe_l, pci_ext_par,`	`pci_ext_ad, pci_ext_cbe_l, pci_ext_par,`
`pci_ext_frame_l, pci_ext_irdy_l,`	`pci_ext_frame_l, pci_ext_irdy_l,`
`pci_ext_devsel_l, pci_ext_trdy_l, pci_ext_stop_l,`	`pci_ext_devsel_l, pci_ext_trdy_l, pci_ext_stop_l,`